Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2008-09-09
2008-09-09
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C375S354000, C327S158000
Reexamination Certificate
active
11080236
ABSTRACT:
A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects each of the transitions of the digital signals. The mode detector determines respective propagation times of the signals through the signal lines based on the relative transitions of the signals. The mode detector then applies delay values to delay circuits that couple the signals to the signal lines with respective delays corresponding to the delay values. The delay values may be determined by coupling a predetermined pattern of test signals through the signal lines and determining which delay values allow the signals to be most accurately captured at the second location.
REFERENCES:
patent: 4481625 (1984-11-01), Roberts et al.
patent: 5086470 (1992-02-01), Ballance
patent: 5243627 (1993-09-01), Betts et al.
patent: 5452333 (1995-09-01), Guo et al.
patent: 5710649 (1998-01-01), Mollenauer
patent: 5802103 (1998-09-01), Jeong
patent: 5956374 (1999-09-01), Iwamatsu
patent: 6010788 (2000-01-01), Kebabjian et al.
patent: 6011441 (2000-01-01), Ghoshal
patent: 6208702 (2001-03-01), Ghoshal
patent: 6211714 (2001-04-01), Jeong
patent: 6316981 (2001-11-01), Rao et al.
patent: 6385367 (2002-05-01), Rogers et al.
patent: 6403887 (2002-06-01), Kebabjian et al.
patent: 6448168 (2002-09-01), Rao et al.
patent: 6452107 (2002-09-01), Kebabjian
patent: 6549059 (2003-04-01), Johnson
patent: 6664839 (2003-12-01), Ootake et al.
patent: 6684030 (2004-01-01), Taylor et al.
patent: 6820234 (2004-11-01), Deas et al.
patent: 6917229 (2005-07-01), Cho
patent: 2004/0223566 (2004-11-01), Yamashita
Greeff Roy
Ovard David
Dorsey & Whitney LLP
Suryawanshi Suresh K
LandOfFree
System and method for reducing jitter of signals coupled... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for reducing jitter of signals coupled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for reducing jitter of signals coupled... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3948176