Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-23
2002-04-30
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
06381719
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a clocking scheme for digital circuits, and more particularly, to a clocking scheme for reducing the clock skew sensitivity of a shift register.
BACKGROUND OF THE INVENTION
Shift registers are well known in the construction of digital circuits. A basic shift register structure comprises a series of flip flops having a common clock input where the output of one flip flop is coupled to the input of the next flip flop. Each flip flop in the shift register has setup time and hold time requirements which define a forbidden zone of the active clock edge, i.e. clock skew, to ensure the correct function of the shift register. In order for a shift register to function properly, the clock skew between a transmitting and a receiving flip flop in a shift register must be less than the intrinsic delay of the transmitting flip flop minus the hold time of the receiving flip flop.
One particular use of such shift registers is for boundary-scan testing, otherwise known as Joint Test Action Group (JTAG). Boundary-scan testing is a non-intrusive method for testing interconnects on printed circuit boards that is implemented at the integrated circuit level. Since its adoption by IEEE as Standard 1149.1, boundary-scan testing has been applied in high volume to high-end consumer products, telecommunication products, defense systems, peripherals, computers and avionics. Current JTAG implementations utilize boundary scan cells coupled to each other so that the cells function as a shift register, and thus are very sensitive to clock skew. A Test Access Port (TAP) controller generates all required control signals for the boundary scan cells including the clock signal. The conventional JTAG clocking scheme routes the JTAG clock as one signal net. However, boundary scan cells need to be placed close to the input or output cell to which it belongs and are therefore distributed along the sides of the die. This distribution causes long net delays which can result in a high skew on a clock net.
As the intrinsic delay in fast sub-micron technologies becomes smaller, it becomes more difficult to achieve the requirements for clock skew. As a result, the use of shift registers in digital circuits, such as for boundary-scan testing, becomes more difficult to implement and increases the effort required during layout resulting in many additional days to complete the layout. Moreover, in some cases it is impossible to achieve the minimum skew required for a secure shift operation of the shift registers. One typical example is a design with several hardmacros (i.e. logic functions with fixed layout, for example Random Access Memories (RAMs)). Ideally, hardmacros should be placed close to the Input/Output (I/O) region of the die in order to easily connect the power rings of the hardmacros to the power rings in the I/O area. This arrangement, however, interferes with the requirement that the boundary scan cells be placed close to the I/O region. For critical outputs (i.e. signals where the delay needs to be as small as possible) the boundary scan cell needs to be placed right next to the output buffer between the I/O area and the hardmacro. This configuration causes big skew on the clock skew since the layout tools can only control the clock skew effectively if there is no blocking area between the clock trunk (placed in the middle of the die) and the flip flop. Because the wire is too long, the skew needs to be balanced manually by slowing down the delay of the other flip flops using balance cells.
SUMMARY OF THE INVENTION
In accordance with the present invention, a system and method for a clocking scheme is implemented to reduce the clock skew sensitivity of a shift register. The system of the present invention advantageously transmits a clock signal through the cells in a shift register in a direction which is against the direction of the data flow of the shift registers. To ensure that the hold time of each cell of the shift register is adequate, a delay circuit is provided in each cell of the shift register to delay the clock signal before transmitting it to the next cell of the shift register. The clocking scheme of the present invention advantageously reduces the sensitivity of the shift register to clock skew and is easy and fast to implement in layout.
The system of the present invention comprises a control circuit, and a first cell and a last cell of the shift register. The control circuit generates a clock signal to the first cell of the shift register. The first cell of the shift register contains a delay circuit for delaying the clock signal before transmitting the clock signal to the next cell of the shift register. The clock signal is continuously delayed by each cell of the shift register as it is transmitted from the first cell to the last cell of the shift register and through the cells of the shift register. The shift register may contain any number of cells, where each cell contains a delay circuit for delaying the clock signal before transmitting it to the next cell in the register. At the same time that the clock signal is transmitted to the first cell of the shift register, a test data circuit line transmits data to the last cell in the shift register. The data is received by the last cell of the shift register and is transmitted through the cells of the shift register in a direction which is against the direction of the clock signal. The present invention also includes a method for reducing the clock skew sensitivity of a shift register. The method includes the steps of generating and transmitting a clocked signal to the first cell of a shift register in a first direction; receiving at the first cell the generated clock signal, delaying the clock signal in the first cell by means of a delay circuit, and transmitting the clock signal to the next cell of the shift register. The method also requires transmitting data to the last cell of a shift register in a second direction which is in the opposite direction of the first direction.
REFERENCES:
patent: 5721740 (1998-02-01), Moon et al.
patent: 5793777 (1998-08-01), Kundu
patent: 5878055 (1999-03-01), Allen
patent: 5909451 (1999-06-01), Lach et al.
Chung Phung M.
LSI Logic Corporation
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