System and method for providing speculative arbitration for tran

Details System and method for providing speculative arbitration for tran System and method for providing speculative arbitration for tran

1997-11-05

2000-04-11

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 27, 710241, G06F 1300

Patent

active

060498455

ABSTRACT:
A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.

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