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Joseph S. Schibinger

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Array for simulating computer functions for large computer syste

Boots – shoes – and leggings
Patent

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Cache-level return data by-pass system for a hierarchical...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Concurrent processing elements for using dependency free code

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Low latency message processor interface using memory mapped Read

Patent

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Mechanism for creating dependency free code for multiple process

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Patent

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Profile ID: LFUS-PAI-P-242199

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