Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-10-24
2003-05-06
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S194000, C365S233100, C365S236000
Reexamination Certificate
active
06560155
ABSTRACT:
TECHNICAL FIELD
The present invention is directed to dynamic random access memory (DRAM) devices, and, more particularly, to a system and method for saving power while refreshing DRAM devices such as programmable conductor DRAM (PCDRAM) devices which only need to be refreshed after an extended interval.
BACKGROUND OF THE INVENTION
Most computers and other digital systems have a system memory which often consists of dynamic random access memory (“DRAM”) devices. DRAM devices are fairly inexpensive because a DRAM memory cell needs relatively few components to store a data bit as compared with other types of memory cells. Thus, a large system memory can be implemented using DRAM devices for a relatively low cost. However, DRAM devices have the disadvantage that their memory cells must be continually refreshed because of the inherently transitory nature of their storage technology.
Generally a DRAM memory cell consists of a transistor/capacitor pair. High and low voltages stored in the capacitor represent logical one and zero data bits, respectively. In a basic DRAM memory cell, one plate of the capacitor is connected to the drain of the transistor, and the other plate is connected to ground. A data bit is written to the cell by enabling the gate of the transistor and applying a voltage corresponding to the data bit to be written to the transistor's source. The enabled transistor conducts the voltage to the capacitor, charging the capacitor and storing the data bit. When the transistor is disabled, the data bit remains stored. Re-enabling the transistor reconnects the capacitor to the source of the transistor, and the stored voltage representing the data bit can be read at the source.
The foregoing is a simplified view, ignoring two considerations presented by the physical nature of the capacitor used in the memory cell. First, a capacitor can hold a voltage only briefly. The smaller the capacitor, the shorter is the duration for which the voltage can be stored. In a DRAM memory device containing thousands of memory cells on a single piece of a semiconductor wafer, these capacitors are infinitesimal, and can only reliably maintain a voltage for microseconds. Consequently, these memory cells must be refreshed thousands of times per second. Second, because these stored voltages dissipate so rapidly, reading the voltage after just a short interval requires a sense amplifier. The use of a sense amplifier is well known in the art to detect whether a stored voltage is high or low, and drive it toward the appropriate binary voltage parameter of the digital device. Fortunately, reading each cell using a sense amplifier not only reads the bit stored in the cell, but also simultaneously refreshes the voltage stored in that cell. The use of sense amplifiers to read and refresh DRAM memory cells is well known in the art. In the interest of brevity, the details of their operation will not be recounted here.
Constantly refreshing DRAM memory cells presents two problems. First, refreshing memory cells slows the useful function of the memory. Memory cells are presented in arrays of rows and columns, often thousands of rows deep and thousands of columns wide. Even though entire rows of an array are refreshed at a time, it still requires thousands of refresh operations to refresh every row in the array. Moreover, these memory arrays cannot be accessed during a refresh cycle. Unless the memory array is equipped with a dual accessing mechanism, a row cache device, or similar means, the array can be neither read from nor written to during a refresh cycle without interrupting or destroying the cycle. If the central processing unit or other controller initiates a memory read or write operation during a refresh cycle, the processor or controller will have to wait for completion of that refresh cycle. This waiting slows processing throughput.
Second, and even more problematic than processing delays, is the power consumed in the continual, rapid refreshing of these memory cells. Thousands of times per second, the gate of each transistor in each memory cell across the entire DRAM array must be activated to refresh the array. Resistance of the conductors through the memory array to address each and every transistor, in each and every row, in each and every column, consumes considerable power. More power is consumed by transistors used in the sense amplifiers which read and refresh the memory cells in respective columns. Still further, supporting circuitry needed to access the rows of memory cells, such as a refresh counter, row multiplexers, row decoders, and address latches, uses even more power.
A simplified view of a typical, conventional DRAM memory array is depicted in
FIGS. 1 and 1A
. Both show part of a 256 Mb array
110
which stores data in two conventional DRAM memory banks
112
and
114
. Each memory bank
112
and
114
, for example, has 8,192 rows of memory cells, for a total of 16,384 rows. The figures are simplified most notably in the sense that they omit components such as column address multiplexers, column address latches, and column decoders. As is well known, reading from or writing to a memory bank requires both a row and a column address to identify the specific memory location where the data is or will be stored. Both row and column addressing circuits are needed to read from and write data to the memory banks. On the other hand, refreshing a memory bank is typically performed by reading and thereby refreshing an entire row at a time across each memory bank, and column addresses are irrelevant. The invention described in this application is directed to a system and method for refreshing a memory array, thus column addressing is not germane. Further discussion of column addressing means has been omitted for the sake of simplicity.
A memory array can be refreshed in either a burst refresh mode or a distributed refresh mode. Using a burst refresh mode, every row of a memory array is sequentially refreshed in rapid succession. Then, after every passage of a predetermined interval, every row of the memory array again is refreshed in rapid succession. The maximum duration of the predetermined interval is the span of time after which the data stored in the DRAM array begins to degrade less the time required to sequentially refresh every row in the array. This standard interval is necessarily brief considering the rapid refreshing needs of a conventional DRAM device.
FIG. 1
depicts a system memory which employs burst refresh. A refresh controller
120
generates a refresh signal after the passage of the predetermined interval. Incremented by each pulse of a refresh clock
122
, a refresh counter
124
sequences through a series of 14-bit binary numbers. The 14-bit binary number equates to one of 2
14
or 16,384 numbers, one of which uniquely corresponds to the address of each row of one of the two memory banks
112
and
114
.
Each row in the memory banks
112
and
114
is accessed through a network of addressing circuitry
160
which includes a row address multiplexer
130
, row address latch A
150
, row address latch B
152
, and row decoders
132
-
142
. Depending upon whether the row address generated by the refresh counter
124
refers to a row in memory bank A
112
or memory bank B
114
, the row address is directed by the row multiplexer
130
to row address latch A
150
or row address latch B
152
, respectively. From the appropriate row address latch
150
or
152
, five bits of the 14-bit address uniquely identify one of the 2
5
or sixteen row decoders
132
-
142
associated with each memory bank. The remaining nine bits of the address uniquely correspond to one of the 2
9
or 512 rows addressed by each row decoder
132
-
142
. Only a few of the sixteen row decoders needed for each memory bank
112
and
114
are shown in the figures for the sake of visual clarity.
After supplying the address of a row to the appropriate memory bank
112
or
114
, that row will be read and thereby refreshed by sense amplifiers incorporated in each memory bank
112
and
114
. In this m
Dinh Son T.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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