Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
2006-08-08
2006-08-08
Pert, Evan (Department: 2826)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S034000, C327S537000, C438S129000
Reexamination Certificate
active
07088131
ABSTRACT:
Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical ‘1’, and for turning on the FET power gate as said disable source goes to a logical ‘0’. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source. A turn on finisher circuit is responsive to the disable signal transitioning to on and to the test signal for holding the power gate solidly on; and a turn off finisher circuit is responsive to the disable signal transitioning to off and to the test signal for holding said power gate solidly off.
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Stout Douglas W.
Windisch, Jr. Charles H.
Beckstrand Shelley
LeStrange Michael J.
Pert Evan
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