Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-11-30
2003-11-11
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S500000, C370S350000, C370S394000
Reexamination Certificate
active
06647504
ABSTRACT:
FIELD OF TECHNOLOGY
BACKGROUND AND SUMMARY
The invention relates to a system and method for generating a real-time signal.
An example of a real-time signal is a clocked stream of audio samples of which should a sample be output every clock period. It is desirable to process such a real-time signal with a modular system in which various separate stations that handle the samples are connected via a bus.
In computer systems arbitrated busses, such as the PCI bus, are a convenient means for communicating information between stations connected to such a bus. For processing real-time signals a complicating factor is that arbitrated busses are variable latency busses. Generally, a variable latency bus has an apriori unpredictable delay between the time the input station first attempts to supply information to the bus and the time when the receiver receives the information. Such an unpredictable delay may for example be caused by arbitration of access to the bus.
For various reasons it is desirable to implement signal processing as much as possible by means of programs in programmable computers, such as a PC. However, in programmable computers the delays are particularly unpredictable, because timing aspects such as delays over the bus are to a large degree made invisible from the program, for example in order not to burden programmers with timing problems.
Even the time value of timers cannot be related to the time of execution of instructions because it is desirable that the timers, which are used in the stations to time the output real-time signal, communicate only via the bus, so as to minimize the connections between the stations.
Amongst others it is an object of the invention to provide for a system for generating a real-time signal using a programmed processor and an output station that are connected via a variable latency bus.
The system according to the invention is set forth in claim
1
.
As a result of using a variable latency bus, a computer program that handles a real-time signal cannot assume that the time at which it executes an instruction to supply sample via a variable latency bus has any fixed relation to the time the sample arrives at its destination station. If the program reads a timer value from another station via a variable latency bus, it cannot be sure of the time point for which this timer value holds.
The problem of an uncertain delay between executing the instruction to supply the sample and its arrival is solved in a known way by adding a so-called time-stamp to the sample. The time stamp represents a time-value of a time counter at which the sample should be reproduced at an output station. The time-stamp makes the exact time of arrival of the sample irrelevant.
However, using a time-stamp means that the program must know the timer value that will be assumed by the output timer of the output station, without being able to read the timer value of the output timer at known time points, due to the variable latency bus. To overcome this problem, the program uses a prediction algorithm for predicting the timer values given time points defined in terms of the signal. Parameters used in this prediction algorithm are for example a factor and an offset between a local time value at a time point and a predicted time value of the output timer at that time point. The program estimates these parameters by reading the timer value of the output timer a number of times via the bus, by comparing the read values to the predicted ones and by adjusting the factor and offset used in the prediction according to the averaged prediction error.
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Cobb, J.A.; Gouda, M.G.; El Nahas, A.; “Time-shift scheduling: fair scheduling of flows in high speed networks” Network Protocols, 1996. Proceedings., 1996 International Conference on , Oct. 29-Nov. 1, 1996 Page(s): 6-13.
Koninklijke Philips Electronics , N.V.
Lee Thomas
Trujillo James K.
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