System and method for multiple cycle capture of chip state

Details System and method for multiple cycle capture of chip state System and method for multiple cycle capture of chip state

2008-01-29

2008-01-29

Maskulinski, Michael C (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S031000

Reexamination Certificate

active

10670620

ABSTRACT:
Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.

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