Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Patent
1997-01-21
2000-11-07
Tokar, Michael
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
365226, 365228, 327530, 327538, H03K 1716, G11C 700
Patent
active
061442194
ABSTRACT:
An isolation mechanism serves to isolate digital signal processor outputs from a dynamic random access memory controller upon the occurrence of a low power condition. The isolation prevents corruption of dynamic random access memory due to low power. The isolation mechanism receives inputs of a first low power indicator and a second low power indicator. The first low power indicator pulls low and the second low power indicator is forced high when a low power condition exists. One embodiment of the isolation mechanism includes a NAND gate connected to a first low power indicator signal and to a second low power indicator signal as inputs, a NOR gate connected with a NAND gate output as input, and a flip flop connected with a NOR gate output and the first low power indicator as inputs. The flip flop output is input to the NOR gate.
REFERENCES:
patent: 4791614 (1988-12-01), Arakawa
patent: 4827149 (1989-05-01), Yabe
patent: 5083293 (1992-01-01), Gilberg et al.
patent: 5206938 (1993-04-01), Fujioka
patent: 5226006 (1993-07-01), Wang et al.
Advanced Micro Devices , Inc.
Tokar Michael
Tran Anh Q.
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