Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-02-15
2003-12-23
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S233100
Reexamination Certificate
active
06667917
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computer memory, and more particularly to systems and methods for identification of faulty or weak memory cells.
2. Description of the Related Art
In the semiconductor industry, embedded memories have become enormously popular as a critical part of Large Scale and Very Large Scale integrated circuits (ICs). Embedded memories allow custom or semi-custom design of ICs that implement part or whole of a system on a chip (SOC), which helps reduce the total component count and manufacturing costs. These ICs also usually employ libraries of “standard cells” as building blocks to construct the desired logic circuits. Standard cells include commonlyused logic functions, such as NOR, NAND, INVERT, and further may also include decoders, registers, counters, and other more complex components.
FIG. 1
is a diagram showing a conventional embedded memory used in IC designs
100
. The memory core includes a memory array
102
having a plurality of memory bit cells
110
. The memory bit cells
110
perform the main function of storing the data in the form of binary logic values of “0” or “1”. Further included is x-decode circuitry
104
, y-decode circuitry
106
, sense amplifier circuitry
109
, I/O circuitry
113
, and control circuitry
108
. The x-decode circuitry
104
and the y-decode circuitry
106
provide the ability to select or access a specific memory cell
110
based on encoded address location provided as input to the embedded memory. The sense amplifier circuitry
109
and the I/O circuitry
113
enable faster access to the selected memory cell
110
. The control circuitry
108
controls the function and timing of the decode circuitry
104
/
106
, sense amp circuitry
109
, and the I/O circuitry
113
by generating internal timing pulses, buffering external input signals and clocks and defining the action to be performed on the memory bit cell. For example, in case of a RAM the action could be a read or a write.
The memory array
102
is generally organized in a two-dimensional array, wherein the memory cells
110
are addressed at the intersection of rows, or “word lines,” and columns, or “bit lines,” of the memory array
102
. To access a given memory cell
110
, it is necessary to select the word line and the bit line at the intersection where the memory element is located. For this purpose, memory addresses are divided into row and column address signals, which are decoded independently using the x-decode circuitry
104
and the y-decode circuitry
106
.
The memory core
100
can include single or multiple configurable memory arrays
102
with identical numbers of rows and columns. Embedded memories are typically designed to provide access to multiple cells
110
in a row in parallel during the same cycle, which is typically defined by the primary clock signal input for the memory. In this case, a plurality of column lines can be grouped together to form an I/O (input/output) memory block array whose column lines are multiplexed into a single I/O by dedicated Y-decode
106
, Sense Amp
109
and I/O
113
circuits. A Memory I/O block then includes the cell array and corresponding Y-decode, Sense Amp and I/O circuitry that will provide access to one single cell
110
per access cycle. In such instance, the memory array
102
contains rows of memory cells
110
that are accessed by activation of the row word line. Groups of these cells are multiplexed into one output, and each such output is accessed concurrently with all the others during the same cycle. Each intersecting point between a row (word line) and an I/O memory block represents the group of memory cells
110
, only one of which is accessed at the I/O pin during a cycle. The collection of these cells in
FIG. 1
form a memory macro unit. One or more of such memory units are used as the principle building block for implementing storage elements on a custom or semi-custom IC or SOC chip.
Although IC Manufacturers strive to produce chips with minimum defects, as a practical matter, defects do occur for various reasons. Such causes can happen during the manufacturing process, such as when random particles of dust settle on the surface of a silicon wafer during processing. Embedded memories are increasingly susceptible to such defects as the density and quantity of memory on ICs increases. The impact of defect within the embedded memories on the overall yield, or the ratio of good parts to total parts, has increased significantly. Since a single defect in a single memory cell can render the whole IC or SOC unusable, techniques to repair such defects by use of extra storage cells have been implemented to improve the overall yield and hence reduce the cost of the IC.
The memory core
100
of
FIG. 1
shows three faulty or weak memory cells
112
. The memory cells
110
that fail to store or retain the correct data altogether are considered faulty or “hard” errors. The memory cells
110
that fail to present correct data in expected time are considered weak or “soft” errors. Weak cells are also memory cells
110
whose performance degrades sufficiently in response to the operating environment such that the memory cells
110
fail to present correct data in expected time.
Such a weak or faulty cell can be caused, for example, by the degradation of the devices, transistors, metal or other bridging defects, defective devices in the cell, or other reasons. Degradation of the devices in the cell can occur from extended use of the memory cell that is coupled with an imperfectly manufactured device. Bridging defects can occur during the semiconductor fabrication process from minor, localized variation in the processing steps like metal deposition or etching. Defective devices in the cell can be the result of undesirable particles that settle onto a semiconductor layer. A single memory cell failure will cause the entire IC or SOC chip to malfunction, and render the chip unusable, unless the defective memory cell can be repaired or replaced to ensure proper functioning of the IC or SOC chip.
Another difficulty arises from packing higher-density building blocks into an IC or SOC chip. Large memory blocks contain a multitude of row memory lines intersecting I/O memory blocks. As a memory array increases in size, the number of correctly functioning memory arrays decreases proportionally, caused by the increasing likelihood of locating memory cell defects within the larger memory array. In order to produce such IC or SOC with large memories while maintaining cost control, some methodology of redundant storage that can be used to repair the defective memories is desirable.
Laser fuse based or other “wired” in repair methods, and built-in self-repair (BISR) methods have been used to repair faulty and weak memory cells via redundant storage elements. Memory cells
112
that prove defective during testing of the memory are replaced by the redundant memory storage elements. Redundancy and repair circuits typically include either laser programmable fuses or other memory elements suitable to store those address configurations that correspond to the defective memory elements and need to be replaced.
Laser programmable fuses have several disadvantages including requiring significant testing and laser programming manufacturing infrastructure. Furthermore, laser programmable fuses are large due to guard ring and other requirements imposed by the laser repair machines. Laser fuse programming does not work correctly 100% of the time, causing additional yield loss. Further, laser programmable fuses must be programmed prior to packaging and therefore all the defects must be identified prior to repair. Identification of the weak cells requires significant additional testing due to their environment dependent nature.
BISR systems use similar approaches. In case of BISR, the circuitry to perform all of the functions is embedded onto the same IC, SOC, or on the same system board, as the memory that may need to be repaired. When these functions are placed outside the IC
Gandhi Dhrumil
Templeton Mark
Artisan Components Inc.
Le Vu A.
Martine & Penilla LLP
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