System and method for generating self-synchronized launch of...

Details System and method for generating self-synchronized launch of... System and method for generating self-synchronized launch of...

2011-07-26

2011-07-26

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07987401

ABSTRACT:
Presented herein are system(s) and method(s) for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing. In one embodiment, there is presented a system for scan testing. The system comprises an ATE clock and a phase lock loop. The ATE clock shifts scan data. The phase lock loop generates capture pulses. The ATE clock or the capture pulses are selected based on an external synchronization signal.

REFERENCES:
patent: 7197725 (2007-03-01), Takeoka et al.
patent: 7380189 (2008-05-01), Konuk
patent: 2002/0136064 (2002-09-01), Yoshiyama
patent: 2003/0009714 (2003-01-01), Evans

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