System and method for forming an inter-layer dielectric in float

Details System and method for forming an inter-layer dielectric in float System and method for forming an inter-layer dielectric in float

1998-12-18

2000-12-19

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438981, H01L 218247

Patent

active

06162683&

ABSTRACT:
A method of forming a floating gate memory device having a memory array region (11), a first periphery region (15), and a second periphery region (17) is provided that comprises forming a polysilicon gate (18) insulatively disposed outwardly from a substrate (10) in the memory array region (11). The polysilicon gate (18) is doped with nitrogen ions. A first oxide layer (20) is formed outwardly from the substrate (10) in the first and second periphery regions (15) and (17) and from the polysilicon gate (18) of the memory array region (11). The thickness of oxide formed outwardly from the substrate (10) is greater relative to the thickness of oxide formed outwardly from the polysilicon gate (18). The first oxide layer (20) in the second periphery region (17) is removed. A second oxide layer (22) is formed outwardly from the substrate (10) of the second periphery region (13), from the first oxide layer (20) in the first periphery region (15) and from the polysilicon gate (18) of the memory array region (11). The thickness of the second oxide layer (22) formed in the first and second periphery regions (15) and (17) is greater relative to the thickness of oxide formed in the memory array region (11).

REFERENCES:
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 5923975 (1999-07-01), Rolandi
patent: 6004847 (1999-12-01), Clementi et al.

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