System and method for forming a uniform thin gate oxide layer

Details System and method for forming a uniform thin gate oxide layer System and method for forming a uniform thin gate oxide layer

1999-06-24

2001-08-28

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S770000, C438S787000, C438S790000, C257S410000, C257S057000

Reexamination Certificate

active

06281138

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuit fabrication and, more specifically, to a system and method for forming a uniform, ultrathin gate oxide layer on a semiconductor substrate.
BACKGROUND OF THE INVENTION
As metal-oxide-semiconductor (“MOS”) technology continues to advance and the features of the MOS devices shrink, a scaling down in the vertical dimension of the devices typically occurs. Critical to the success of these devices is a reliable, highquality gate-dielectric with a low defect density (“D
o
”) and a high breakdown field strength (“F
bd
”) that retains its quality during advanced processing. As the overall thickness of the gate dielectric gets ultrathin (e.g., less than 7.5 nm), the quality of the oxide (e.g., SiO
2
), even under the best possible external growth conditions, is limited by the natural viscoelastic compressive stress generated in the SiO
2
at temperatures below 1000° C. and by the thermal expansion mismatch between silicon substrate and SiO
2
. In present applications, a genuine lowering of the D
o
in the range of 0.05 to 0.5 cm
−2
has been achieved. For example, oxide
itride or oxide
itride/oxide (ONO) structures can attain such low D
o
. The Si
3
N
4
—SiO
2
(“silicon nitride-silicon oxide”) interface, however, is invariably associated with a high density of interface states (“Q
it
”) that cannot be annealed out easily because the Si
3
N
4
layer is impervious to diffusion of oxidizing species. These multi-layered dielectrics are unsuitable as gate dielectrics in advanced complementary metal-oxide-semiconductor (“CMOS”) integrated circuits, because the interface states may cause charge-induced shift in the threshold voltage and can reduce the channel conductance during operation.
To overcome this problem, the concept of stacking thermally grown and chemical-vapor-deposited (“CVD”) SiO
2
structures has been proposed in U.S. Pat. No. 4,851,370 (“the '370 patent”), which is incorporated herein by reference for all purposes. Here, the composite stack is synthesized by a 3-step grow-deposit-grow technique wherein the growing steps are conducted at pressures equal to or greater than one atmosphere. The interface between the grown and deposited SiO
2
layers serves the same purpose as the interface in SiO
2
—Si
3
N
4
structures (i.e., it reduces the D
o
by misaligning the defects across the interface). Moreover, the interface traps in stacked oxide structures that can be removed easily by an oxidizing anneal, since the top deposited SiO
2
layer, unlike the Si
3
N
4
film, is transparent to oxidizing species (i.e., it transports them by diffusion). This stacking concept can be applied to any composite dielectric structure with similar results as long as the top deposited dielectric layer is transparent to the oxidizing species.
A few major factors contributing to defects in conventional thin-oxide gate dielectrics are growth-induced micropores and intrinsic stress within the oxide layer. The micropores are 1.0 nm to 2.5 nm in diameter, with an average separation of about 10.0 nm. The pores form at energetically favored sites such as heterogeneities created by localized contaminants, ion-damaged areas, dislocation pileups and other defect areas on the silicon surface resulting from retarded oxidation in these sites. The pores grow outward as oxidation continues to consume silicon around the pore. Thus, a network of micropores usually exists in SiO
2
. The micropore network forms potential short-circuit paths for diffusional mass transport and for current leakage.
In addition, the stress within a SiO
2
layer, often accentuated by complex device geometries and processing, usually increases both the size and density of the micropores. Therefore, in developing thin dielectrics with ultra-low D
o
, not only should the initial D
o
be reduced, but also the local stress-gradients near the Si—SiO
2
interface should be reduced by providing a stress-accommodating layer, such as an interface (between grown and deposited layers) within the dielectric that acts as a stress cushion and defect sink.
The above-mentioned problems become even more acute as the overall size of devices decrease to sub-micron size with ultrathin gate dielectrics (e.g., less than 7.5 nm). Unfortunately, however, the above-discussed conventional stacked-oxide process, which works extremely well in technologies where the gate dielectric thickness is greater than 7.5 nm, is not as applicable in technologies having thicknesses less than 7.5 nm. The main reason for this is that in the conventional 3-step stacked process, the SiO
2
is grown in pressures of one atmosphere or greater. In semiconductor technologies where the gate oxide thickness is 10.0 nm or greater, this particular condition is most advantageous because under such atmospheric pressure, the SiO
2
can be grown quite rapidly and one can grow the first grown layer (typically 1.0-7.5 nm) with good uniformity. This rapid growth is highly desirable, for it cuts down in manufacturing time, and thus, overall production costs. This same rapid growth, which is so advantageous in technologies with gate oxide thickness of 10.0 nm or greater is less desirable in sub-0.5 micron semiconductor technologies because the oxides grow too quickly, which makes thicknesses harder to control. As such, the oxide layers are less uniform in thickness, which is unacceptable.
Furthermore, performance degradation of these devices that occurs with time, which is often referred to as the hot carrier (electron or hole) degradation effect, is also well known. It is believed that this efficiency degradation is caused by defects that are generated by the current flow through the device. It is believed that these defect states reduce the mobility and lifetime of the carriers and cause degradation of the device's performance. In most cases, the substrate comprises silicon, and the defects are thought to be caused by dangling bonds (i.e., unsaturated silicon bonds) that introduce states in the energy gap, which remove charge carriers or add unwanted charge carriers in the device, depending in part on the applied bias. While dangling bonds occur primarily at surfaces or interfaces in the device, they also are thought to occur at vacancies, micropores, dislocations, and are also thought to be associated with impurities. To alleviate the problems caused by such dangling bonds, a hydrogen passivation process has been adopted and has become a well-known and established practice in the fabrication of such devices.
In the hydrogen passivation process, it is thought that the defects that affect the operation of semiconductor devices are removed when the hydrogen bonds with the silicon at the dangling bond sites. While the hydrogen passivation process eliminates the immediate problem associated with these dangling bonds, it does not eliminate degradation permanently because the hydrogen atoms that are added by the passivation process can be “desorbed” or removed from the previous dangling bond sites by radiation or by the “hot carrier effect.”
A hot carrier is an electron or hole that has a high kinetic energy that is imparted to it when voltages are applied to the electrodes of the device. Under such operating conditions, the hydrogen atoms, which were added by the hydrogen passivation process, are knocked off by the hot electrons, and result in aging or degradation of the device's performance. According to established theory, this aging process occurs as the result of hot carriers stimulating the desorption of hydrogen from the silicon substrate's surface or SiO
2
interface. This hot carrier effect is particularly of concern with respect to smaller devices.
Accordingly, what is needed in the art is a stacked-oxide process that provides gate dielectrics having thickness than 10.0 nm and, more advantageously less than 7.5 nm, and yet provides a semiconductor that has a low defect density (“D
o
”) and a high breakdown field strength (“F
bd
”) that retains its quality during advanced

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