Chemistry: electrical and wave energy – Apparatus – Coating – forming or etching by sputtering
Reexamination Certificate
2001-05-21
2004-01-06
Zarabian, Amir (Department: 2822)
Chemistry: electrical and wave energy
Apparatus
Coating, forming or etching by sputtering
C257S618000, C257S619000, C257S622000
Reexamination Certificate
active
06673220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a system and method for forming silicon targets for use in sputter deposition processes.
2. Description of the Related Art
Research continues into methods of producing polycrystalline (p-Si) film by annealing amorphous silicon (a-Si) films. Polycrystalline films are used in the formation of IC active areas, such as the source, drain, and gate regions of a transistor. One specific application is the formation of thin film transistors (TFTs) that are used in the fabrication of active matrix (AM) liquid crystal displays (LCDs).
One relatively recent approach to forming an amorphous silicon film is through silicon (Si) sputter deposition. Little prior art exists in this field, as the application of sputtering method for silicon deposition in microelectronics (i.e. TFTs) is quite new. There is a body of work in the use of silicon targets for sputtering of optical coatings (SiO2, SiNx), but this application differs. The optical coatings are particularly valued for their optical characteristics, not their electrical characteristics. In some circumstances these optical coating targets are heavily doped to improve conductivity of the resulting film. However, a highly doped silicon film cannot be formed into a transistor active area. Furthermore, these optical coatings are a continuous blanket films and, therefore, little regard is paid to particle size and uniformity. Transistor active area silicon films are patterned, however, often to small geometries. Therefore, the particle composition, of little regard in a blanket optical coating film, is critical in the formation of transistor silicon film.
FIGS. 1
a
through
1
e
are partial cross-sectional diagrams illustrating the fabrication of a conventional top-gate TFT structure (prior art). Poly-Si (polycrystalline-Si) TFTs are made by a plurality of processes. In the majority of polycrystalline silicon TFT LCD applications, the so-called top-gate, polycrystalline silicon TFT structure is used. Typically, Plasma-Enhanced Chemical Vapor Deposition (PE-CVD) or Low-Pressure CVD (LPCVD) is used to deposit the amorphous silicon precursor. There are several advantages in using physical vapor deposition (PEV) or sputtering to form the silicon film. Such advantages are a reduction in process steps, as there is no need for dehydrogenation, equipment cost reduction, and improved process safety, since no toxic/pyrophoric gases are necessary.
In
FIG. 1
a
a barrier layer
10
is deposited over a substrate
12
. Amorphous silicon is deposited over barrier layer
10
and annealed, using an Excimer Laser for example, to form polycrystalline silicon layer
14
.
In
FIG. 1
b
the polycrystalline silicon layer
14
is patterned and dry etched.
In
FIG. 1
c
a gate isolation layer
16
is formed over the polycrystalline silicon layer
14
. A gate
18
is formed over gate isolation layer
16
, and the source region
20
and drain region
22
are implanted with P material.
In
FIG. 1
d
an interlayer dielectric
24
is isotropically deposited.
In
FIG. 1
e
the interlayer dielectric
24
is selectively etched to form vias to the source/drain regions
20
/
22
. A source contact
26
and a drain contact
28
are deposited and patterned. The present invention is concerned with the sputter deposition of the amorphous silicon used to from polycrystalline silicon layer
14
(
FIG. 1
a
).
FIG. 2
is a partial cross-sectional diagram of a typical DC magnetron sputtering chamber (prior art). One of the key aspects of the silicon-sputtering process is the ‘target’ component. The target is a block of the material to be deposited, mounted on an appropriate metal backing plate, and placed opposite to the substrate where the film is to be deposited. Plasma strikes in the gap between the target and the substrate. The magnet that is scanning above the target backing plate is used to intensify the plasma and confine it in the region defined by the magnetic field. By scanning the magnet, the plasma is swept across the surface of the target, resulting in deposition of the film on the substrate opposite to the target. The plasma is generated by applying high voltage to an inert gas (typically Ar, but alternately He, Ne, Kr or mixtures) that flows in the region between the target and the substrate. For certain applications, other gases may be mixed to the sputtering gas, such as H2, O2, N2, etc., to alter the composition and/or the properties of the sputtered film.
The target is an important component of the sputtering process because it affects the level of contamination in the film, as well as the level of particles, which are generated during the deposition process. Particles are fragments of silicon material that are detached from the target material during processing. Particles larger than approximately 5 microns are not desirable in TFT process films. Hence, the target manufacturing must proceed in a way that the produced target can yield low levels of contamination in the deposited film as well as a low level of particles. High particle levels result in low yields, as well as reduced equipment up-time, since frequent cleaning of the chamber is required. Film contamination needs to be reduced below acceptable levels, for the films to be suitable for the fabrication of electronic devices.
The issue of particles is particularly severe for silicon targets for two reasons: (1) the target is a tiled assembly (not a single piece), which means that the edges of the tiles can generate particles, unless they are properly prepared; and, (2) the target material is generally of low resistivity (does not conduct thoroughly) as a result of the purity requirements of the deposited film. Hence, the material is susceptible to charge buildup and, consequently, arcing, especially if the surface of the target is not properly conditioned. Arcing may result in increased contamination in the film, especially with the material that the chamber and internal components being made of Al, Ni, or equivalent metals.
It would be advantageous if a process existed for efficiently sputtering silicon to form an amorphous silicon film.
It would be advantageous if the amorphous silicon film could be sputter deposited without particle contaminants.
It would be advantageous if silicon targets existed that minimized contamination in the sputter deposition of amorphous silicon film.
SUMMARY OF THE INVENTION
The present invention involves a procedure to produce silicon targets for use in microelectronics, particularly in the fabrication of polycrystalline silicon TFTs. The silicon tiles and resultant targets demonstrate excellent particle performance and reduced contamination levels in the deposited silicon-films.
Accordingly, a method is provided for forming silicon target tiles in the fabrication of integrated circuit (IC) sputter deposited silicon films. The method comprises: cutting either single-crystal or polycrystalline silicon tiles to a thickness in the range of 7 millimeters (mm) to 10 mm; and, treating the silicon tile edges to minimize the generation of contaminating particles. The silicon tile treatment includes subjecting the silicon tile top and bottom surface edges to a beveling or radiusing operation. The silicon tile top surface edges are beveled within the range of 1 mm to 5 mm, or radiused within the range of 3 mm to 10 mm. The silicon tile bottom surface edges are beveled approximately 1.5 mm. Further, the silicon tile treatment includes beveling the silicon tile corners approximately 1.5 mm.
The method further comprises: chemically etching the silicon tile surfaces to remove silicon material within the range of 50 microns (um) to 500 um; polishing the silicon tile top and bottom surfaces to a predetermined flatness in the range of 0.1 um to 10 um; and, attaching a plurality of the polished silicon tiles to a backing plate to form a completed silicon target.
Additional details of the above-described silicon tile target fabrication method an
Hartzell John
Voutsas Apostolos
Krieger Scott C.
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
Soward Ida M.
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