System and method for fabricating a fin field effect transistor

Details System and method for fabricating a fin field effect transistor System and method for fabricating a fin field effect transistor

2006-08-22

2010-06-29

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S700000, C257SE21428

Reexamination Certificate

active

07745319

ABSTRACT:
There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.

REFERENCES:
patent: 5021353 (1991-06-01), Lowrey et al.
patent: 5177027 (1993-01-01), Lowrey et al.
patent: 5804506 (1998-09-01), Haller et al.
patent: 6060783 (2000-05-01), Juengling et al.
patent: 6110798 (2000-08-01), Gonzalez et al.
patent: 6346455 (2002-02-01), Thakur et al.
patent: 6376380 (2002-04-01), Tang et al.
patent: 6469389 (2002-10-01), Juengling et al.
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6903425 (2005-06-01), Tang et al.
patent: 6936507 (2005-08-01), Tang et al.
patent: 7071043 (2006-07-01), Tang et al.
patent: 7071049 (2006-07-01), Tang et al.
patent: 7265059 (2007-09-01), Rao et al.
patent: 2002/0179970 (2002-12-01), Yagishita et al.
patent: 2004/0191980 (2004-09-01), Rios et al.
patent: 2004/0251487 (2004-12-01), Wu et al.
patent: 2005/0035391 (2005-02-01), Lee et al.
patent: 2005/0110085 (2005-05-01), Zhu et al.
patent: 2005/0179030 (2005-08-01), Seo et al.
patent: 2005/0205945 (2005-09-01), Lee
patent: 2005/0266638 (2005-12-01), Cho et al.
patent: 2005/0275040 (2005-12-01), Anderson
patent: 2006/0043449 (2006-03-01), Tang
patent: 2006/0043450 (2006-03-01), Tang et al.
patent: 2006/0043471 (2006-03-01), Tang et al.
patent: 2006/0046391 (2006-03-01), Tang et al.
patent: 2006/0046424 (2006-03-01), Chance et al.
patent: 2006/0063350 (2006-03-01), Chance et al.
patent: 2006/0125044 (2006-06-01), Haller
patent: 2006/0151880 (2006-07-01), Tang et al.
F. Fishburn, B. Busch, J. Dale, D. Hwang, R. Lane, T. McDaniel, S. Southwick, R. Turi, H. Wang, and L. Tran, A 78nm 6F2 DRAM Technology for Multigigabit Densities, Micron Technology, Inc. — Process R&D Center, Boise, Idaho.
T. Park, S. Choi, D.H. Lee, J.R. Yoo, B.C. Lee, J.Y. Kim, C.G. Lee, K.K. Chi, S.H. Hong, S.J. Syun, Y.G. Shin, J.N. Han, I.S. Park, U.I. Chung, J.T. Moon, E. Yoon, and J.H. Lee, Fabrication of Body-Tied Fin FETs (Omega MOSFETs) Using Bulk Si Wafters, 2003 Symposium on VLSI Technology Digest of Technical Papers.
R. Katsumata, N. Tsuda, J. Idebuchi, M. Kondo, N. Aoki, S. Ito, K. Yahashi, T. Satonaka, M. Morikado, M. Kito, M. Kido, T. Tanaka, H. Aochi and T. Hamaoto, Fin-Array-FET on Bulk Silicon for Sub-100 nm Trench Capacitor DRAM, 2003 Symposium on VLSI Technology Digest of Technical Papers.
J.C. Sturm and K. Tokunaga, Increased Transconductance in Fully-Depleted Ultra-Thin Silicon-on-Insulator Mosfet's, Department of Electrical Engineering, Princeton University, Princeton, NJ.
Leland Chang, Yang-Kyu Choi, Daewon Ha, Pushkar Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Hu, and Tus-Jae King, Extremely Scaled Silicon Nano-CMOS Devices, IEEE, vol. 91, No. 11, Nov. 2003, pp. 1860-1873.

Affiliated with

Also associated with

Rating

System and method for fabricating a fin field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for fabricating a fin field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for fabricating a fin field effect transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4225971