Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-01-27
2001-12-04
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S501000, C713S503000
Reexamination Certificate
active
06327666
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data communications, and more particularly, to a system and method for achieving timing synchronization by providing external timing using a complex rotator.
BACKGROUND OF THE INVENTION
In the field of data communications a transceiver, or modem, is used to convey information from one location to another. Digital Subscriber Line (DSL) technology now enables transceivers to communicate rapidly large amounts of data. Transceivers communicate by modulating a baseband signal carrying digital data, converting the modulated digital data signal to an analog signal, and transmitting the analog signal over a conventional copper wire pair using techniques that are known in the art. These known techniques include mapping the information to be transmitted into a multi-dimensional multilevel signal space constellation and slicing the received constellation to recover the transmitted information. The constellation can include both analog and digital information or only digital information.
In the above mentioned communications environment, a control transceiver is located at a telephone company central office location. Connected to the transceiver via a conventional copper wire pair is a remote transceiver. The remote transceiver resides at a location, such as a residence or a business location. Before the central office transceiver can exchange information with the remote transceiver, clock timing and synchronization between the central office transceiver and the network master clock must be established.
Timing and synchronization are fundamental to any digital transmission and switching network. In a digital transmission system, timing is encoded with the transmitted signal using the network master clock, such as a T1 or E1 clock. As such, the central office transceiver must recover system timing and synchronization from this system clock. Once frequency synchronization between the central office transceiver and the network clock is achieved, the receiver in the transceiver can identify frame boundaries of the receive and transmit data signal.
In the aforementioned communications environment, synchronization is provided in a master-slave relationship such that the network, T1 for example, timing is at the highest level allowing it to provide timing to all transmission systems that are connected to the network. Each transceiver connected to the network must be synchronized to the network system clock.
A common technique for achieving timing synchronization between the network clock and the central office transceiver is based upon the use of an external framer which performs bit/pulse stuffing. In this arrangement the aggregate bit stream has a higher data rate than the input data rate from the network. This arrangement allows the accommodation of additional stuffing and framing bits. The stuffing bits are inserted or deleted in the incoming data stream until the clock rate is equal to that of the input rate, or its frequency is locked to the system clock. The stuffed bits are inserted at fixed locations of each frame so that they can be identified and removed at the remote transceiver. Unfortunately, this technique requires the use of additional bits that consume bandwidth and reduce the aggregate data rate.
Another known technique for achieving network timing synchronization is to lock the central office transceiver to the system clock using a voltage controlled oscillator (VCO) in conjunction with a phase locked loop (PLL). In this arrangement, timing lock is achieved by tuning the local frequency of a VCO using an additional phase and frequency measurement circuit that adjusts the transceiver reference frequency to lock a local reference clock to the system clock. This is achieved by measuring the offset between the system clock and a reference clock in order to develop an error signal to supply to the PLL which in turn drives the VCO. This technique uses additional circuitry that adds system cost and complexity.
Thus, it would be desirable to allow a central office transceiver to achieve timing lock and synchronization to a system clock without the need to transmit additional bits or without requiring costly additional circuitry.
SUMMARY OF THE INVENTION
The present invention provides an improvement to synchronizing the clock of a transceiver to a network system clock by allowing the transceiver to synchronize to the network system clock without the use of any external framing or circuit componentry.
This task is accomplished by providing a system for providing external timing which includes a filter configured to receive a sampled clock signal input and to provide a two dimensional multilevel signal output. This two dimensional multilevel signal output is then supplied to a demodulator configured to multiply the two dimensional multilevel signal output with a complex rotation signal and provide an output in the form of a phase error signal. The phase error signal is then supplied to a loop filter configured to operate on the error signal to develop and output a real voltage signal to a frequency synthesizing device. The frequency synthesizing device is configured to supply its output to the system clock. The system clock supplies a signal to a complex generator which outputs the complex rotation signal. The complex rotation signal is designed to control the demodulator such that the resultant error signal output from the demodulator provides information regarding the rotation of the clock signal. The system clock is also configured to output the signal used to drive the sample rate of the input clock and a baud clock signal, which is at the desired rate to enable timing synchronization between the transceiver and the system clock.
In a first alternate embodiment, a bit rate multiplier configured to multiply the input clock signal to an integer ratio of the input clock is included. In a second alternate embodiment, a divider configured to divide the input clock signal to a rate proportional to that of the input clock is included.
The present invention also provides a method for providing external timing by supplying to a filter a sampled clock signal input. The filter is configured to receive the sampled clock signal input and to provide a two dimensional multilevel signal output. The clock signal input is sampled at a particular rate determined by a sampling signal developed by the invention. The two dimensional output of the filter is demodulated with a complex rotation signal resulting in a phase error signal output. The phase error signal is supplied to a loop filter resulting in a real voltage output. The real voltage output of the loop filter is supplied to a frequency synthesizing device, which in turn supplies its output to the system clock. The system clock supplies a signal to a complex generator which outputs a complex rotation signal. The complex rotation signal controls the demodulator, thus providing the error signal output. The system clock develops the sampling clock signal, which is used to sample the input clock signal prior to the complex filter and also provides the baud clock signal, which is at the desired rate to enable timing synchronization between the transceiver and the system clock.
In a first alternate embodiment, a multiplier configured to multiply the input clock signal to a rate proportional to that of the input clock is included. In a second alternate embodiment, a divider configured to divide the input clock signal to a rate proportional to that of the input clock is included.
The invention has numerous advantages, a few of which are delineated hereafter, as merely examples.
An advantage of the present invention is that it eliminates the need to send additional stuffing and framing bits to synchronize the transceiver clock to the system clock.
Another advantage of the invention is that it can be implemented completely within a digital signal processor (DSP).
Another advantage of the invention is that it can be adapted to work on a wide range of system clock speeds and ratios.
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Gut Richard
Langberg Ehud
Wang Chenshu
Butler Dennis M.
Globespan, Inc.
Thomas Kayden Horstemeyer & Risley
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