System and method for executing loops in a processor

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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Reexamination Certificate

active

07991984

ABSTRACT:
A loop control system comprises at least one loop flag in an instruction word, at least one loop counter associated with the at least one loop flag operable to store and compute a number of times a program loop is to be executed, at least one start address register associated with the at least one loop flag operable to store a program loop starting address, and at least one end address register associated with the at least one loop flag operable to store a program loop ending address.

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Singh et al., Interconnect Pipelining in a Throughput-Intensive FPGA Architecture, Feb. 2001, pp. 153-160.

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