System and method for exclusively writing tag during write alloc

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711119, 711143, 711144, G06F 1208

Patent

active

057874697

ABSTRACT:
Implemented within a computer system, a cache memory element having a cache hierarchy including a first level cache and at least a second level cache. In the event that a processor core requests a copy of a selected cache line and intends to modify contents of the selected cache line and the selected cache line cannot be supplied by the first or second level cache, tag information is solely written into the second level cache and higher level caches. This preserves databus bandwidth and enhances performance of the computer system.

REFERENCES:
patent: 5251308 (1993-10-01), Frank et al.
patent: 5555392 (1996-09-01), Chaput et al.
patent: 5561779 (1996-10-01), Jackson et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5627992 (1997-05-01), Barro

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