System and method for erase test of integrated circuit...

Details System and method for erase test of integrated circuit... System and method for erase test of integrated circuit...

2005-11-15

2005-11-15

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06966016

ABSTRACT:
A system and method for testing a flash memory device having uniform sectors and smaller, “boot” sectors includes determining uniform and boot test limits. The uniform and boot test limits are determined based on average erase and APDE time periods of the uniform and boot sectors, respectively. In this way, the erase test results for each sector type is compared against test limits that are based only on that sector type, thereby avoiding excessive false rejects.

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