System and method for encoding constant operands in a wide...

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing

Reexamination Certificate

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C712S024000

Reexamination Certificate

active

06922773

ABSTRACT:
For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

REFERENCES:
patent: 4109310 (1978-08-01), England et al.
patent: 4595911 (1986-06-01), Kregness et al.
patent: 6006324 (1999-12-01), Tran et al.
patent: 6173305 (2001-01-01), Poland
patent: 6282633 (2001-08-01), Killian et al.

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