System and method for electronic device development

Details System and method for electronic device development System and method for electronic device development

2011-07-26

2011-07-26

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07987399

ABSTRACT:
A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

REFERENCES:
patent: 5592077 (1997-01-01), Runas et al.
patent: 6630754 (2003-10-01), Pippin
patent: 6810497 (2004-10-01), Yamada
patent: 2004/0268181 (2004-12-01), Wang et al.

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