Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2005-06-07
2005-06-07
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C455S114200, C455S110000, C455S115100, C375S298000
Reexamination Certificate
active
06904538
ABSTRACT:
The present invention is directed towards a data detector for deriving a data signal from an incoming radio frequency input. The data detector comprises a delay logic which receives an unfiltered signal in quadrature and in-phase components, and applies a delay to each of the in-phase and quadrature phase components of the unfiltered input signal. The detector further comprises a first multiplication logic that multiplies the delayed in-phase component of the unfiltered signal by the quadrature phase component of the unfiltered signal to obtain a first result, and a second multiplication logic that multiplies the delayed quadrature phase component of the unfiltered signal by the in-phase component of the unfiltered signal to obtain a second result. Finally, an adder adds the first result with the second result to generate a data signal. In alternative embodiments a post detection correction algorithm may be added to improve performance.
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Glas Jack P.
Prodanov Vladimir I.
Agere Systems Inc.
Elamin A.
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