Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Forming nonplanar surface
Reexamination Certificate
2002-02-27
2003-12-09
Schilling, Ronald L. (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Forming nonplanar surface
C430S326000, C430S331000
Reexamination Certificate
active
06660459
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates generally to fabrication processes for integrated circuits (IC). More specifically, the present specification relates to an improved system for and method of developing a photoresist layer on a semiconductor substrate.
BACKGROUND
The semiconductor industries continue to manufacture semiconductor integrated circuits with higher and higher densities on a smaller chip area. The desire for large scale integration has led to a continued shrinking of the circuit dimensions and features of the devices so as to reduce manufacturing costs and to improve circuit functionality. The ability to reduce the size of structures such as gate lengths in field-effect transistors is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current IC fabrication processes, optical devices expose the photoresist to light having a wavelength of 248 nm (nanometers). Research and development laboratories are experimenting with light having a wavelength of 193 nm. Further, the next generation lithographic technologies will in all likelihood progress toward a radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Extreme Ultra-Violet (EUV) lithography (e.g., 13 nm).
In a conventional lithographic process, after a semiconductor wafer is coated with photoresist and exposed to light with a circuit pattern, developer is applied to the photoresist to remove portions of the photoresist. The developer is removed with a water rinse and dried by a spinning process before subsequent etching.
One obstacle to the further reduction in printed feature size is the pattern collapse between photoresist lines or other photoresist features caused by the water rinse and drying step.
FIGS. 1 and 2
illustrate the problems caused by this conventional technique. In
FIG. 1
, a wafer
10
is shown having photoresist lines
12
. Rinse water
14
is illustrated after the rinsing step and just prior to drying. The inherent cohesive and adhesive forces of water create surface tension between photoresist lines
12
as the water evaporates. During the drying step, as shown in
FIG. 2
, fine photoresist lines
12
are pulled laterally by the surface tension, causing pattern collapse and ruining the resulting etch.
Currently, pattern collapse is avoided by limiting the printed feature size. One proposed solution is to freeze-dry a rinse liquid (i.e., tert-butanol). However, this method is time consuming, resulting in decreased throughput. Although the method could be done in batch processing, this adds complexity to the process. Another proposed solution is to use perfluorohexane as a rinser. However, perfluorohexane is difficult to dispose of. If pattern collapse can be reduced or eliminated, narrower features can be printed, thereby enabling higher microprocessor speeds and higher device density on the substrate.
Accordingly, there is a need for an improved system for and method of developing a photoresist layer. Further, there is a need for a system for and method of developing a photoresist layer to reduce or eliminate pattern collapse. Further still, there is a need for a system for and method of reducing surface tension caused by the water rinse during photoresist development. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
SUMMARY OF THE INVENTION
According to an exemplary embodiment, a method of developing a photoresist layer on a semiconductor wafer in a developing chamber includes applying a developer to the photoresist layer, applying an evaporating solution to the photoresist layer, and drying the photoresist layer.
According to another exemplary embodiment, a method of patterning a photoresist layer on a semiconductor wafer includes exposing the photoresist layer to light, developing portions of the photoresist layer with a photoresist developer, whereby photoresist lines remain on the wafer, rinsing the developed portions of the photoresist layer with an alcohol rinse, and drying the wafer.
According to yet another exemplary embodiment, an integrated circuit on a semiconductor substrate includes devices fabricated by a photolithographic process including the steps of: applying a photoresist layer to the semiconductor substrate; exposing the photoresist layer to light; developing portions of the photoresist layer with a photoresist developer, whereby photoresist lines remain on the wafer, rinsing the developed portions of the photoresist layer with an alcohol rinse, and drying the wafer.
REFERENCES:
patent: 5374502 (1994-12-01), Tanaka et al.
patent: 5678116 (1997-10-01), Sugimoto et al.
patent: 6451510 (2002-09-01), Messick et al.
patent: 6554507 (2003-04-01), Namatsu
patent: 3-209715 (1991-09-01), None
patent: 7-106226 (1995-04-01), None
patent: 7-122485 (1995-05-01), None
patent: 8-62859 (1996-03-01), None
“Aqueous-based Photoresist Drying using Supercritical Carbon Dioxide to Prevent Pattern Collapse” by Goldfarb, et al., 2000 American Vacuum Society, J. Vac. Sci. Technolog. B 18(6), Nov./Dec. 2000.
“Comparison of Resist Collapse Properties for Deep Ultraviolet and 193 nm Resist Platforms” by Cao, et al. 2000 American Vacuum Society, J. Vac. Sci. Technol. B 18(6), Nov./Dec. 2000.
“Sub-0.1 &mgr; m Patterning with High Aspect Ratio of 5 Achieved by Preventing Pattern Collapse” by Yamashita Jpn. J. Appl. Phys. vol. 35 (1996) pp. 2385-2386, Part 1, No. 4A, Apr. 1996.
“X-Ray Lithography with a Wet-Silylated and Dry-Developed Resist” by Oizumi, et al., Jpn. J. Appl. Phys. vol. 34 (1995) pp. 6734-6737, Part 1, No. 12B, Dec. 1995.
“Prevention of Resist Pattern Collapse by Flood Exposure During Rinse Process” by Tanaka, et al., Jpn. J. Appl. Phys. vol. 33 (1994) pp. L1803-L1805, Part 2, No. 12B, Dec. 15, 1994.
“Sub-100 nm Focused Ion Beam Lithography Using Ladder Silicone Spin-on Glass” by Suzuki, et al., 1996 American Vacuum Society, J. Vac. Sci. Technol. B 14(6), Nov./Dec. 1996.
“Freeze-Drying Process to Avoid Resist Pattern Collapse” by Tanaka, et al., Jpn. J. Appl. Phys. vol. 32 (1993) pp. 5813-5814, Part 1, No. 12A, Dec. 1993.
“Mechanism of Resist Pattern Collapse During Development Process” by Tanaka, et al., Jpn. J. Appl. Phys. vol. 32 (1993) pp. 6059-6064, Part 1, No. 12B, Dec. 1993.
“Mechanism of Resist Pattern Collapse” by Tanaka, et al., J. Electrochem Soc., vol. 140, No. 7, Jul. 1993.
“Patterning Characteristics of a Chemically-Amplified Negative Resist in Synchrotron Radiation Lithography” by Deguchi, et al., Jpn. J. Appl. Phys. vol. 31 (1992) pp. 2954-2958, Part 1, No. 9A, Sep. 1992.
“Collapse Behavior of KrF Resist Line Pattern Analyzed with Atomic Force Microscope Tip”, by Kawai, Jpn. J. Appl. Phys. vol. 39 (2000) pp. 7044-7048 Part 1, No. 12B, Dec. 2000.
“Analysis of Resist Pattern Collapse and Optimization of DUV Process for Patterning sub-0.20 &mgr; m Gate Line” by Yu, et al., SPIE vol. 3333, pp. 880-889.
“Pattern Collapse in the Top Surface Imaging Process After Dry Development” by Mori, et al., 1998 American Vacuum Society, J. Vac. Sci. Technol. B 16(6), Nov./Dec. 1998.
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