System and method for determining on-chip bit error rate...

Details System and method for determining on-chip bit error rate... System and method for determining on-chip bit error rate...

2006-08-15

2006-08-15

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S704000, C375S221000, C370S249000

Reexamination Certificate

active

07093172

ABSTRACT:
A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.

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Definition of an OSI Layer 1 device, at http://en.wikipedia.org/wiki/OSI—model, accessed on Sep. 14, 2005.

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