System and method for determining integrated circuit logic...

Details System and method for determining integrated circuit logic... System and method for determining integrated circuit logic...

2005-11-15

2005-11-15

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S141000, C365S233100

Reexamination Certificate

active

06966022

ABSTRACT:
An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal is then asserted at the reset pin, and a reset time is measured. The reset time is defined as the time period beginning when the reset signal is asserted and ending when the storage element resets. In this manner, the reset time can be used to determine a speed of the IC logic relative to a process. In one aspect, delay logic is provided that is in electrical communication with the reset pin and in electrical communication with the storage element. In this aspect, the delay logic delays the reset signal for a predetermined time period. Optionally, the reset time can be compared to a predetermined fast corner reset time and a predetermined slow corner reset time. Further, the IC logic speed can be correlated to a simulation using the embodiments of the present invention.

REFERENCES:
patent: 5959487 (1999-09-01), Kawamura
patent: 6414903 (2002-07-01), Keeth et al.
patent: 2002/0188899 (2002-12-01), Yamazaki
patent: 04331383 (1990-12-01), None
patent: 04350580 (1991-05-01), None
“Picoseconds Measurement of Internal Waveforms in Integrated Circuits Using Sampling Force Probing. I. Principle and Demonstration” Said, R.A. International Symposium on Circuits and Systems, ISCAS 2000 Publication: May 28-31, 2000 p. 681-684 vol. 2.

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