Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-01
2010-11-02
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S700000, C714S712000, C714S724000, C365S201000, C324S765010
Reexamination Certificate
active
07827455
ABSTRACT:
The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write address counter that is clocked by the data strobe is used to count the active edges of the data strobe. A read address counter that is periodically synchronized with the write address counter, but that is clocked by an internal clock of the receiver, is used to count units of data being received from the interface. Periodically, the contents of the read and write counters are compared. If the contents are not the same, a glitch has occurred on the data strobe. The glitch is recoverable if it occurs on, or after, a last strobe edge of a data transfer.
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Eckel Nathan A.
Levinshteyn Peter
Lucas Gary J.
Gaffin Jeffrey A
Marley Robert P.
Merant Guerrier
Unisys Corporation
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