Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-20
2007-03-20
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10817132
ABSTRACT:
A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.
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Babcock Carl
Capodieci Luigi
Haidinyak Chris
Kim Hung-eil
Lukanc Todd P.
Advanced Micro Devices , Inc.
Garbowski Leigh M.
Winstead Sechrest & Minick P.C.
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