Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-28
2011-06-28
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S739000
Reexamination Certificate
active
07971119
ABSTRACT:
A method for defect-based scan analysis comprises, determining a neighborhood net for a circuit node, injecting defects into the neighborhood net, modeling the defects with stuck-at-0 and stuck-at-1 fault models, generating and applying test patterns to the neighborhood net, determining whether the injected defects are observable as faults, adding the test patterns to a set of effective test patterns if the defects are observable, mapping the test patterns to possible stuck-at-0 faults or stuck-at-1 faults, collecting stuck-at-0 and stuck-at-1 fault test patterns, performing stuck-at-0 and stuck-at-1 fault simulations using the stuck-at-0 and stuck-at-1 fault test patterns, respectively, generating first and second fault lists, combining first and second fault lists into combined fault lists, deriving a description of the combined fault lists using a complete set of fault models, filtering the combined fault lists to yield a collection of effective faults, and determining a defect for each of the effective faults.
REFERENCES:
patent: 5291495 (1994-03-01), Udell, Jr.
patent: 5377197 (1994-12-01), Patel et al.
patent: 5410548 (1995-04-01), Millman
patent: 5938785 (1999-08-01), Dargelas
patent: 6044214 (2000-03-01), Kimura et al.
patent: 6957403 (2005-10-01), Wang et al.
patent: 2004/0064773 (2004-04-01), Kundu et al.
patent: 2004/0237012 (2004-11-01), Prasad et al.
patent: 2005/0166114 (2005-07-01), Buckley
patent: 2006/0005094 (2006-01-01), Nozuyama
patent: 2006/0053357 (2006-03-01), Rajski et al.
patent: 2006/0259842 (2006-11-01), Marinissen et al.
Aitken, “Finding Defects with Fault Models”, International Test Conference (26th: 1995: Washington, D.C.), pp. 498-505.
Zijiang Lin, et al., “High-Frequency, At-Speed Scan Testing,” Co-published by the IEEE CS and the IEEE CASS, Sep.-Oct. 2003, pp. 17-25.
Vamsi Boppana, et al., “Modeling the Unknown! Towards Model-Independent Fault and Error Diagnosis,” International Test Conference (29th: 1998: Washington, D.C.), pp. 1094-1101.
Robert C. Aitken, “Finding Defects with Fault Models,” International Test Conference (26th: 1995: Washington, D.C.), pp. 498-505.
Patrick Girard, et al., “High Defect Coverage with Low Power Test Sequences in a BIST Environment,” IEEE Design & Test Special Issue on Defect Oriented Testing in Deep Submicron Era, Sep./Oct. 2002 (vol. 19, No. 5) pp. 44-52.
Rene David, “Random Adjacent Sequences: An Efficient Solution for Logic BIST,” IFIP Conference Proceedings; vol. 218, Publisher: Kluwer, B.V. Deventer, The Netherlands, pp. 1-12.
aiwan Semiconductor Manufacturing Company, Ltd.
Gaffin Jeffrey A
Haynes and Boone LLP
McMahon Daniel F
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