System and method for current-enhanced stress-migration...

Details System and method for current-enhanced stress-migration... System and method for current-enhanced stress-migration...

2005-03-15

2005-03-15

Sarkar, Asok Kumar (Department: 2829)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C324S071100, C438S014000, C438S468000

Reexamination Certificate

active

06867056

ABSTRACT:
For testing for stress-migration failure of interconnect, an interconnect test structure is formed with a first feeder line coupled to a test line by a first no-flux structure, and with a second feeder line coupled to the test line by a second no-flux structure. A respective width of ea ch of the first and second feeder lines is greater than a width of the test line. A resistance meter and a timer measure a stress-migration life-time of the interconnect test structure with a current being continuously conducted through the interconnect test structure that is continuously heated to a predetermined temperature.

REFERENCES:
patent: 5712510 (1998-01-01), Bui et al.
patent: 5900735 (1999-05-01), Yamamoto
patent: 6320391 (2001-11-01), Bui
E.T. Ogawa et al.,Stress-Induced Voiding under Vias Connected to Wide Cu Metal Leads,IEEE International Reliability Physics Symposium, 2002.

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