Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-12
2002-04-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06367051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit design tools. In particular, the present invention relates to design tools which optimize area, performance, and power for integrated circuits.
2. Discussion of the Related Art
The interconnection wiring (“interconnect”) among circuit elements in an integrated circuit is expected to dominate signal delays and to limit achievable circuit density of an integrated circuit. Existing design methods, which treat interconnect as “parasitics” and focus on optimizing transistors and logic gates, are ill-equipped to provide a design which delivers the necessary performance. Typically, in a conventional design method, the circuit elements of an integrated circuit are first synthesized and placed. A routing tool is then used to interconnect these circuit elements. Interconnect signal propagation problems are identified during routing, when the interconnect dominates the delay. Because placement and routing are performed relatively independently, adding buffers and repeaters to correct these interconnect signal propagation problems identified during routing is a costly iterative process.
Various techniques have been applied to address signal propagation performance in an integrated circuit design. For example, U.S. Pat. No. 5,638,291, entitled “Method and Apparatus for Making Integrated Circuits by Inserting Buffers into a Netlist to Control Clock Skew” to Li et al., discloses modification of a net list to insert buffers into clock signal paths to control clock skew. As another example, U.S. Pat. No. 5,396,435, entitled “Automated Circuit Design System and Method for Reducing Critical Path Delay Times” to Ginetti, discloses modification to a logic circuit to reduce delays in a critical path of an integrated circuit. However, the effectiveness of these methods for increasing circuit performance is constrained by their inability to concurrently affect placement of circuit elements.
SUMMARY OF THE INVENTION
The present invention provides a method for mapping circuit elements of a net list onto a physical design. The method includes the steps of: (a) partitioning the physical design area into multiple bins; (b) mapping the circuit elements into the multiple bins; (c) inserting a buffer between each pair of connected circuit elements placed in bins more than a predetermined distance apart; (d) optimizing placements of the circuit elements and the buffers in the physical design by revising the mapping of the circuit elements and the buffers to the bins in accordance with a cost function; and (e) subdividing the bins and remapping circuit elements into the subdividing bins, while inserting or removing appropriately buffers and shielding buffers, where appropriate.
In one embodiment, the predetermined distance for buffer insertion is the minimum of either the distance at which the propagation delay of the buffer substantially equals the delay provided by an interconnect wire of a predetermined width over the distance, or the distance for which the signal attenuation exceed a predetermined value. In one application, a buffer is inserted concurrently with placement to both reduce the delay to a far away load and to shield the far away load from the nearby load. In another application, a buffer is inserted in a critical path both to reduce the delay in the critical path and to isolate the critical path from other loads on the same net.
The present invention can be used in conjunction with many design tools, including a placement tool which provides successively smaller bins for placement, and repeats optimizing placement and interconnect steps and buffer removing steps at every level of partitioning.
In one embodiment, until predetermined criteria are met, buffers inserted are held in a virtual buffer list outside of the input circuit net list. The buffer is incorporated into the net list when the distance between the pair of connected circuit elements interconnected by the inserted buffer exceeds a distance determined based on the current bin size. The buffer is removed from the virtual list when the pair of connected circuit elements become separated by less than a predetermined distance.
The present invention is applicable not only to conventional design with conventional interconnect, but also in design such as those with copper interconnect or design interconnected by RF transmission lines carrying high speed mixed mode signals. The present invention is also applicable to integrated systems design, such as design of a micromachine including electronic circuits.
REFERENCES:
patent: 4593363 (1986-06-01), Burnstein et al.
patent: 5396435 (1995-03-01), Ginetti
patent: 5452239 (1995-09-01), Dai
patent: 5638291 (1997-06-01), Li et al.
Boyle Douglas B.
Chakraborty Abhijeet
Malik Sharad
Odabasioglu Altan
Pileggi Lawrence
Do Thuan
Hallman Jon W.
Monterey Design Systems, Inc.
Skjerven Morrill & MacPherson LLP
Smith Matthew
LandOfFree
System and method for concurrent buffer insertion and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for concurrent buffer insertion and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for concurrent buffer insertion and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2892323