Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-03-16
2003-06-10
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C710S071000
Reexamination Certificate
active
06578153
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to communications link calibration and specifically to a system and method for communications link calibration using a training packet.
BACKGROUND OF THE INVENTION
The present invention is applicable in any field where high speed data transfer occurs such as telecommunications, data communications, high speed computing and disk drives. In these types of systems, it is often necessary to transfer data across a communications link that operates at a higher speed than the receiver interface. One way to accomplish this goal while maintaining the same level of bandwidth is to use parallel communications links at a slower speed. For example, assume the first data rate is four times greater than the second data rate. In that case, using four parallel links at the lower rate will provide equivalent bandwidth to one link at the higher rate.
Serial-to-parallel converters that perform this demultiplexing function are known in the art. These converters include circuitry that transfers each serial bit to one of a number of parallel outputs. These parallel outputs can be provided to additional circuitry in the system. Such a configuration is shown in
FIG. 1
, which includes serial-to-parallel converter
10
and processing circuitry
12
.
To ensure that processing circuitry
12
is receiving valid data from serial-to-parallel converter
10
, a calibration sequence can be used. In this example, controller
14
issues commands to stop communication and begin the calibration sequence. A known sequence can then be provided to the input line of the serial-to-parallel converter
10
. Processing circuitry
12
can look for this known sequence and make any necessary adjustments in order to correct for errors.
This solution, however, is not ideal since it requires that communications between serial-to-parallel converter
10
and processing circuitry
12
be shut down during the calibration process. In some applications, such as in telephone or data networks, this requirement may not be acceptable.
SUMMARY OF THE INVENTION
The present invention provides an improved system and method for calibrating a serial to parallel link. The preferred embodiment uses a training packet. Training packets allow a handshake free method to correct for logical versus physical link effects. These effects might include data structure independent demultiplexing and timing or “bit slips” amongst multiple physical links.
In a first aspect, the present invention provides a method of correcting space errors in a plurality of parallel data streams. In this method, n streams of parallel data are received, for example, at a receiver in a fiber optic transmission system. The receiver circuitry searches through the n streams of parallel data to detect a unique characteristic that is possessed by one of the streams of data but not any of the other streams of data. Based on this unique characteristic, one of the streams of data is assigned to a particular bit position within n bit positions. The other streams of data can the be assigned different ones of the n bit positions.
This aspect of the present invention is useful to simplify the framing process. Space errors can be caused, for example, by the conversion of serial data into parallel data. Using this technique provides a simple and inexpensive way to detect word boundaries in that situation.
In another aspect of the present invention, time errors (e.g., bit position errors) can be corrected in a plurality of parallel data streams. In this method, n streams of parallel data are received, possibly from circuitry that has already performed word alignment as described above. Each of the streams is in a particular pattern. For each of the n streams of parallel data, a characteristic, e.g., a pattern change such as a transition, is detected in the particular pattern and, using this characteristic, the n streams can be re-timed relative to one another.
Various aspects of the present invention include a number of advantages over prior art techniques. For example, the present invention can be implemented in a uni-directional or bi-directional channel. No network control is required. In addition, the method can be implemented in a way that is handshake free. This technique can also be easily extended to include links with parity bits.
Aspects of the method are advantageous because the framing process is simplified and there is no need to shut down then communications link when the method is used. This packet has use in a great number of applications. One prime example is in dense wavelength division multiplexed (DWDM) system where the bandwidth across the fiber is very high.
The preferred embodiment of the present invention is also very inexpensive in terms of system bandwidth. For example, in some applications much less than 0.001% of the total available bandwidth will be consumed by the training packet. In addition, in this embodiment the link remains operational when being trained.
REFERENCES:
patent: 5253254 (1993-10-01), Roberts et al.
patent: 5426784 (1995-06-01), Kawata et al.
patent: 5455830 (1995-10-01), Gregg et al.
patent: 6031767 (2000-02-01), Schuh et al.
patent: 6134247 (2000-10-01), Solana de Quesada et al.
patent: WO 98/37494 (1998-08-01), None
International Search Report in International Application No. PCT/US 01/08226, dated May 7, 2002, 6 pages.
Koyuncu Osman
Li Kam-Wing
Sankey Wayne Robert
Scott Kyl
Sojitra Ritesh Dhirajlal
Baker & Botts L.L.P.
Fujitsu Network Communications, Inc.
Lee Thomas
Suryawanshi Suresh K
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