Static information storage and retrieval – Read/write circuit – Multiplexing
Reexamination Certificate
2002-05-08
2004-03-23
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Multiplexing
C365S154000, C365S230040
Reexamination Certificate
active
06711067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of memory logic devices and more specifically to memory devices having multiple banks of memory arrays. More particularly, the present invention relates to memory arrays that allow for bit line sharing.
2. Description of the Background Art
Memory devices are well known in the semiconductor industry. Memory cores for integrated circuits continue to be improved. Because of the proliferation and popularity of Application Specific Integrated Circuits (ASIC) and systems-on-a-chip, there is a need for improved designs for memory arrays. New memory arrays are needed because of the ever decreasing size and power requirements. For example, new uses for ASICs such as cellular telephones, portable computers, and hand held devices require new memory arrays that require less circuit area to implement, and consume less power to extend battery life.
One approach used in the conventional systems is to provide ultra low power and high-speed memory devices has been to use multiple banks of memory arrays. A conventional multiple bank memory is shown in FIG.
1
. As can be seen, the multiple bank memory includes an X-decoder
108
, control and pre-decoding logic
120
, and pairs of reference columns
102
,
114
, memory cell arrays
104
,
112
, word line drivers
106
,
110
, pre-charge circuits and Y-decoders or multiplexors
116
,
122
, and sense amplifiers and input/output (I/O) circuits
118
,
124
. While the conventional systems provide some power reduction and speed improvement, they suffer from a number of problems.
For instance, consider FIG.
2
.
FIG. 2
illustrates a conventional memory cell array
200
. Memory cell array
200
includes rows
210
and columns
220
of memory cells
230
, a word line
240
for each row
210
, and two bit lines
250
,
260
for each column
220
. As shown in
FIG. 2
, the conventional memory cell array
200
utilizes two bit lines
260
(x),
250
(x+1) side by side in order to retrieve data from two adjacent memory cells
230
(x),
230
(x+1). By requiring two separate bit lines, memory cell array
200
is restricted as to the amount it can be reduced to fit today's smaller size requirements. This size restriction is due to a need for a dead space between bit lines
260
(x) and
250
(x+1) to avoid negative effects due to an increase in capacitance and electro-magnetic interference between the lines.
The prior art also typically requires that all bit lines
250
,
260
in all arrays
104
,
112
, be pre-charged. In the multi-array implementation illustrated in
FIG. 1
, this requirement consumes power by pre-charging a set of bit lines for each memory array
104
,
112
. By way of example, at the beginning of a read cycle, the bit lines in both first memory array
104
and second memory array
112
are pre-charged. Assuming that the read address is resolved to be in first memory array
104
, the charge on the bit lines in second memory array
112
is inefficient and wastes power.
Therefore, there is a need for a system and method for constructing multiple bank memory cell arrays that are smaller in size, consume less power, and reduce electrical interference.
SUMMARY OF THE INVENTION
The present invention overcomes the limitations of conventional systems by providing a memory device in which adjacent memory cells share a bit line. In particular, memory cells from two separate memory arrays, or planes are alternately placed in a row so that each cell is adjacent to a cell from the other memory plane. These adjacent cells share a bit line thereby reducing the number of bit lines to be pre-charged as well as reducing the spacing cost associated with conventional cell column layouts.
In one implementation the memory device includes a first memory cell, a second memory cell, an even word line, an odd word line, and a shared bit line. The first memory cell is configured to store and retrieve a first data value, and the second memory cell is configured to store and retrieve a second data value. The odd word line is connected to the first memory cell to access the first memory cell, and the even word line is connected to the second memory cell to access the second memory cell. The shared bit line is connected to an output on both the first memory cell and the second memory cell. The memory device may also include a sense amp connected to the shared bit line to generate an output based data retrieved from the first and second memory cells. The memory device also includes a Y-inverter which is configured to selectively invert the data retrieved from the first and second memory cell depending on which cell is accessed.
In another implementation, the memory device includes a third and fourth memory cell, and a second and third shared bit lines. The second shared bit line is connected between an output on the second and third memory cells, and the third shared bit line is connected between an output on the third and fourth memory cells. In one embodiment, the memory device further includes a Y-multiplexor connected to receive data from the first, second and third shared bit lines. The Y-multiplexor is configured to selectively choose a subset of the bit lines as an output based on which memory cells are accessed. In one embodiment, the Y-multiplexor is a 3:2 MUX, and may be comprised of a plurality of transistors. In another embodiment, the memory device may include a sense amp connected to the output of the Y-multiplexor to receive selected subset of bit lines to generate an output. Additionally, an inverter may be coupled to the output of the sense amp to selectively invert the output based on which memory cells are accessed.
In yet another embodiment, the arrangement of the first, second, third and fourth memory cells and first, second, and third shared bit lines is extended to include any number of memory cells and shared bit lines. Additionally, Y-multiplexors, sense amps, and Y-inverters may also be provided to receive the data from the additional bit lines and memory cells similar to the embodiments discussed above.
In still another embodiment, a memory device utilizing shared bit lines also uses word line banking to further extend the space and power savings by combining two or more bit-line-shared arrays into a single cascaded memory array utilizing word line banking.
Other aspects of the invention include a method relating to the devices described above.
One advantage of the present invention is that it reduces the number of bit lines and attendant circuitry by about half, as well as reduces the power consumed in pre-charging the bit lines.
REFERENCES:
patent: 5276650 (1994-01-01), Kubota
patent: 5995419 (1999-11-01), Trimberger
patent: 6243287 (2001-06-01), Naffziger et al.
Fenwick & West LLP
Hoang Huan
Virage Logic Corporation
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