Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-24
2006-01-24
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06990619
ABSTRACT:
A system for automatically retargeting test vectors for application on tester systems having different performance capabilities is provided. The system includes a user selectable mode selector that can be adjustable between different performance modes, e.g. high, medium, and low. In high performance mode, the system allows test vectors to be applied using a high performance test system, e.g. a tester having high pin count. In low performance mode, the same test vectors can be applied but using a low performance test system, e.g. a tester having low pin count. By allowing the same test vectors to be used in a high performance or a low performance test environment, a testing facility can make maximum use of its available testing equipment for efficiently testing a device.
REFERENCES:
patent: 5983380 (1999-11-01), Motika et al.
patent: 6311300 (2001-10-01), Omura et al.
Kapur Rohit
Williams Thomas
Bever Hoffman & Harms LLP
De'cady Albert
Harms Jeanette S.
Kerveros James C.
Synopsys Inc.
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