Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-02-15
2005-02-15
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000, C714S033000
Reexamination Certificate
active
06857090
ABSTRACT:
A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results. The system also includes raw data generating means for generating raw data on the basis of time data occurring when the test process is performed; data calculating means for calculating testing time data, index time data based on the raw data, and loss time data; data storage means for storing the raw data and the calculated data; and data analyzing and outputting means for analyzing the raw data and the calculated data according to the lots, the plurality of testers and the IC device loading/unloading means and for outputting the analyzed output through an user interface. The test system includes testers, a server system and terminal computer, and the server system is provided with data storage means for integrally manipulating time data generated by the testers according to lots and test cycles and for storing manipulated time data.
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Chung Ae Yong
Kim Sung Ok
Lee Kyu Sung
Tu Christine T.
Volentine & Francos, PLLC
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