System and method for automatic masking of compressed scan...

Details System and method for automatic masking of compressed scan... System and method for automatic masking of compressed scan...

2006-11-28

2006-11-28

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000, C714S738000

Reexamination Certificate

active

07143324

ABSTRACT:
A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e., masking signal) to mask bits in an unbalanced scan chain. In one embodiment, the control signal is generated with a logic gate, a comparator, and a counter.

REFERENCES:
patent: 6346822 (2002-02-01), Nishikawa
patent: 6543018 (2003-04-01), Adusumilli et al.
patent: 7058869 (2006-06-01), Abdel-Hafez et al.

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