System and method for alleviating skew in a bus

Details System and method for alleviating skew in a bus System and method for alleviating skew in a bus

1998-03-02

2000-08-15

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

713503, G06F 112

Patent

active

061051446

ABSTRACT:
In order to transmit several data words in succession over a bus between components in a data processing system, the skew between the various bus lines has to be compensated in order that each data word is accurately received. The skew compensation is implemented by setting predetermined delays on certain bus lines in response to the comparison of a test pattern with an ideal situation.

REFERENCES:
patent: 5608896 (1997-03-01), Vogley
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5872959 (1999-02-01), Nguyen et al.
patent: 5923198 (1999-07-01), Fujioka
Natsuki Kushiyama et al., A 500-Megabyte/s Data-Rate 4.5M DRAM, IEEE Journal of Solid State Circuits, Bol. 28, No. 4, Apr. 1993, pp. 490-498.

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