System and method for aligning a quadrature encoder and...

Details System and method for aligning a quadrature encoder and... System and method for aligning a quadrature encoder and...

2005-12-15

2008-12-02

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S047300, C714S700000, C714S703000, C714S704000, C714S705000, C714S707000, C714S709000, C714S731000, C714S744000, C714S755000, C714S746000, C714S798000, C375S226000, C375S225000, C375S235000, C370S215000, C370S236200, C370S241100, C370S242000, C370S324000, C702S089000

Reexamination Certificate

active

07461317

ABSTRACT:
A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.

REFERENCES:
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patent: 2004/0021632 (2004-02-01), Lou
patent: 2004/0025097 (2004-02-01), Lou
patent: 2005/0228654 (2005-10-01), Prieto et al.

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