Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-07-05
2011-07-05
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
07975194
ABSTRACT:
A system comprises a decompressor that receives an input test vector and generates an output vector in response to the input test vector. A decoder couples to the decompressor and comprises a reset pattern detector (RPD), a lookup table, and control logic. RPD scans the output vector to identify a predetermined reset pattern. The control logic couples to the RPD and the lookup table and directs operation of the lookup table in a first or second mode based on whether the output vector comprises the predetermined reset pattern, as identified by the RPD. The lookup table receives the output vector, to operate in the first mode, storing one of a plurality of codeword sets, each codeword set comprising a plurality of pairs of codewords and associated data; and to operate in the second mode, generating test data blocks in response to identified codewords in the output vector.
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Caldwell, Esq. Patrick E.
Chung Phung M
International Business Machines - Corporation
The Caldwell Firm, LLC
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