Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1997-08-26
1998-09-22
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518523, 36523006, G11C 1140
Patent
active
058124632
ABSTRACT:
The present invention provides a high speed, high voltage latch that minimizes leakage current and vulnerability to latch-up. The latch has a switching transistor between a program power supply and the output. The switching transistor is turned off by the latch input when the latch input transitions so as drive the output to a low level. The switching transistor thereby minimizes leakage current. An output driver transistor coupled to the program power supply is used. The latch output is initially pulled up through a Vcc power supply. The output driver transistor turns on after the latch output has been pulled up to an initial level. The output driver transistor then pulls up the output terminal to the high output voltage level through the program power supply. Pulling up the output initially with the Vcc power supply minimizes the device power dissipation. The latch circuit further comprises two program power supplies to prevent latch-up, an n-well power supply and a local power supply. When the latch is switched from read mode to program mode the n-well power supply is raised to the program voltage before the local power supply is raised. When the latch is switched from program mode to read mode the n-well power supply voltage is not reduced until after the local power supply has been reduced and the rest of the circuit has discharged. This ensures the n-well voltage is at least as high as the voltage of the p-diffusions coupled to the n-well and thereby prevents latch-up.
REFERENCES:
patent: 5365479 (1994-11-01), Hoang et al.
patent: 5396459 (1995-03-01), Arakawa
patent: 5455789 (1995-10-01), Nakamura et al.
Bluestone Randall J.
Integrated Silicon Solution Inc.
Le Vu A.
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