Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-11-30
2002-07-23
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S194000
Reexamination Certificate
active
06424583
ABSTRACT:
TECHNICAL FIELD
The present invention broadly relates to built in self test modules for integrated circuits (IC's), and deals more particularly with a system for determining the access time of memories embedded in the IC.
BACKGROUND OF THE INVENTION
As deep submicron ASIC applications (Applications Specific Integrated Circuit) and IC technology continue to evolve, the chips forming these devices contain greater numbers of embedded memories. Constant improvements in memory technology, including dynamic random access memory (DRAM) and static random access memory (SRAM) are providing more bits per chip. This increase in the number of bits stored on a single chip means that there is a corresponding increase in the number of memory cells and circuits that need to be tested per chip. Access times for DRAMs and SRAMs have also become shorter. This places demands on testing for higher speeds of operation.
In order to conform the functionality of chips before they are shipped, electronic testers are employed to test the functionality of each chip with the increasing complexity of IC circuitry and density, and shorter access times for memories, the testers must operate at higher frequencies and signal rates in order to confirm the faster operation of the chips.
In the past, chips have been tested using external automatic test equipment at the manufacturing site. These external test systems employ an external test pattern as a stimulus, and apply the patterns to the chips under test. The tester examines the chip's response, and compares it against known responses stored as part of the test pattern data. Because of the time required to connect and disconnect each chip to the external tester, the semiconductor manufacturing industry has resorted to so-called built in self tests (BIST) modules that are placed directly on the IC chip. BIST modules consist of circuitry formed on the chip that surrounds the device or circuit under test. Typical BISTs implement a finite state machine (FSM) to generate a test stimulus. This test stimulus is applied to the device or circuit under test, and the response is then analyzed and compared against reference standards. The BIST module therefore typically includes a controller, a data generator and a data analyzer. This module interfaces with higher level systems on the chip. In a system mode of operation, system data is passed directly to core circuitry (in the case of a memory), essentially bypassing the BIST module. However when switched to a test mode, the BIST module is activated to perform self test functions on a device, such as an SRAM, in order to perform a pass/fail test program. Common tests performed by BIST modules include a Marching test, a Checkerboard test, or a unique address test. A number or other tests are possible, but in any event, following each test, a pass/fail result is delivered from the BIST to the tester.
As IC's become more widespread and embedded core memories possess shorter access times, it becomes more difficult to accurately measure access times, even using a BIST module. Further complicating the task of measuring access times is that the margins between signals continue to decrease as the overall speed of chip circuitry continues to increase. As will be discussed later in more detail, the current technique for measuring access time of embedded core memories is a trial and error approach in which a test must be repeated many times in order to determine the precise relative timing of signals that reveal the access time of each memory address.
It would therefore be desirable to provide a BIST module that automatically measures embedded memory access time more accurately during a shorter test intervals compared to prior memory test systems and BIST modules. The present invention is directed toward satisfying this need.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a system is provided for determining the access time of a memory forming part of an integrated circuit. The system includes a built in self test circuit formed on the integrated circuit chip for testing a memory, and means on a chip coupled with the BIST for measuring the access time of the memory. The measuring means includes logic means coupled with the BIST and the memory for operating on data represented by “1's” and “0's” bits accessed from a memory, and delay means for delaying the delivery of the data from the memory to the logic means. The logic means include separate sets of logic circuits for operating on the data respectively represented by the
“0's” and “1's”. The delay means includes first and second sets of delay elements for delaying the delivery of the “1's” and “0's” to the corresponding logic circuits. The BIST preferably includes a finite state controller for controlling the state of the BIST, a pattern generator for generating a patterned stimulus to be applied to the memory and a comparator for comparing the response of the memory to the stimulus to a referenced response.
According to another aspect of the invention, a method is provided for determining the access time of a memory forming part of an integrated circuit. The method broadly includes the steps of writing data into the memory at a first memory address; commencing a read cycle in which data is read from the memory at the first address; introducing a time delay in the data being read; determining the total time required to read the data from the memory at the first address location; and, calculating the access time based on the total time and the delay time. The introduction of a time delay in reading the data is preferably achieved by passing the read data through a delay element.
REFERENCES:
patent: 6266749 (2001-07-01), Hashimoto et al.
Chang Meng-Fan
Chen Hsien-Te
Sung Nai-Yin
Wu Tsung-Yi
Le Vu A.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung Randy W.
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