System and controller with reduced bus utilization time

Details System and controller with reduced bus utilization time System and controller with reduced bus utilization time

2005-01-28

2009-06-02

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C365S189020, C365S189070

Reexamination Certificate

active

07543114

ABSTRACT:
A memory controller may reduce bus utilization time. The memory controller may include a main controller, a data reading unit, and a serial interface. The main controller may store a control data signal received from a processor through a bus, and may control a memory by generating a request data signal, which may be based on the stored control data signal. The data reading unit may store read address signals, which may be received from at least one of the processor and IP blocks through another bus, and may read data from the memory by generating a command data signal, which may be based on the stored read address signal. The serial interface may interface at least one of the main controller and the data reading unit with the memory. The memory controller may reduce the utilization time of a bus by more efficiently controlling data reading and/or writing operations of the memory.

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