System and circuit for ASIC pin fault testing

Details System and circuit for ASIC pin fault testing System and circuit for ASIC pin fault testing

1997-11-17

1999-11-09

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714724, G01R 3128

Patent

active

059833777

ABSTRACT:
A system and circuit for pin fault testing is disclosed. The system includes an external tester and a circuit designed to be tested. The external tester is coupled to pins of the circuit and is configured to enter test data into the circuit. The external tester is also configured to receive continuity data from the circuit and to determine pin faults from a comparison of the test data to the continuity data. The circuit includes a plurality scan cells which are coupled in a chain fashion. When testing input pins, the external tester places a test pattern onto the input pins, stores a continuity pattern into the scan cells that are electro-mechanically coupled to the input pins, serially scans the continuity pattern out of the circuit, and compares the continuity pattern to the test pattern. When testing the output pins, the external tester serially scans a test pattern into the scan cells coupled to the output pins and compares the continuity pattern generated on the output pins to the test pattern.

REFERENCES:
patent: 4791359 (1988-12-01), Raymond et al.
patent: 5383195 (1995-01-01), Spence et al.
patent: 5406216 (1995-04-01), Millman et al.
patent: 5425034 (1995-06-01), Ozaki
patent: 5434804 (1995-07-01), Bock et al.
patent: 5450415 (1995-09-01), Kamada
patent: 5477545 (1995-12-01), Huang
patent: 5504432 (1996-04-01), Chandler
patent: 5513186 (1996-04-01), Levitt
patent: 5546406 (1996-08-01), Gillenwter et al.
patent: 5596585 (1997-01-01), Njinda et al.
patent: 5907562 (1999-05-01), Wrape et al.

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