Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-14
2006-11-14
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07137054
ABSTRACT:
A system and method for scan testing an NCDL and latches controlled by the NCDL is presented. The NCDL is controlled by control logic, a switch is used to control the latches by a clock signal that is not controlled by the control logic. A controllability circuit provides test vectors to, and controls, the NCDL. The outputs of the NCDL are observed by an observability circuit that captures the outputs of the NCDL.
REFERENCES:
patent: 6286118 (2001-09-01), Churchill et al.
patent: 6286119 (2001-09-01), Wu et al.
Ali Syed Mohammed
Bindus Ravindra
Pande Anand
Srinivas Koppineedi Naresh Chandra
Valmiki Ramanujan K.
Broadcom Corporation
De'cady Albert
Kerveros James C.
McAndrews Held & Malloy Ltd.
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