Synthesizable synchronous static RAM

Details Synthesizable synchronous static RAM Synthesizable synchronous static RAM

2001-11-20

2002-10-22

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06470475

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of electronic circuits, and, more particularly, to a synthesizable, synchronous static random access memory (RAM) for use in application specific integrated circuits (ASICs).
BACKGROUND OF THE INVENTION
The complexity of ASIC chips is continually increasing. Most ASICs include built-in memory. One memory commonly used on ASICs and system on chips (SOCs) is static random access memory (SRAM). There are two types of SRAMs commonly in use, namely synchronous and asynchronous SRAMs. The operations inside the asynchronous memories are not synchronized to a clock, while in synchronous memories all operations are synchronized to a clock signal. The SRAMs used in ASICs are typically optimized for high speed, low power, and small areas and are synchronous in nature.
A typical prior art synchronous SRAM may include a data input port, an address port, a clock port, a memory select port, an output enable port, a write enable port, and an output port. See, e.g., Handy, Jim, “The Cache Memory Book”, Academic Press, Inc., Harcourt Brace & Company. The structure of one such synchronous prior art SRAM is illustrated in
FIG. 1
, which includes a decoder section
1
.
1
, a core section
1
.
2
, an input/output (IO) section
1
.
3
, control and clock generation circuits
1
.
4
, and dummy paths (not shown).
The above listed blocks or elements are made in the form of bit slice cells that are abutted to form a memory block of a desired word of x-bit configuration. Development of the memory may include making these cells in a particular technology and “tuning” them according to the full range of words and bits required. Typically a critical path is used for scheduling various operations, which are triggered by the positive edge of the external clock. This critical path may be characterized on CAD tools to tune the memory for different shapes and sizes. See, e.g., Weste Neil H. E., Eshraighian Kamran, “Principles of CMOS VLSI Design: Systems Perspective”.
There are also self-timing structures which use a dummy path along the core and are triggered at the positive edge of the internal clocks (generated by the clock generation circuits). Such structures are used to switch off the sense amps and initialize pre-charging at a suitable time (after the read/write operation has ended). See Handy, above. This saves power consumption and decreases the cycle time of the memory.
Current designs of such memories have several drawbacks. First, the memory cells are full custom blocks that do not follow standard cell design rules and hence cannot be used along with the standard cells. They are, therefore, treated as “hard core” macros for which separate planning has to be done in the layout process, which may require a considerable amount of time for certain technologies. Furthermore, the testability is poor as the standard design for testability (DFT) tools treat these custom cells as “black boxes” and hence do not model internal structure.
Another drawback may be the fact that such memories may not have an asynchronous reset facility and therefore require a long time for initialization. Additionally, these memories are typically routed in more than three metal layers. Thus, over-the-block routing in metal in higher levels is not possible. Also, the front end models in hardware-description language HDL's are based upon the custom designs, and thus the method of operation of the memory may not be clear to the user. This can make debugging of such memories difficult.
SUMMARY OF THE INVENTION
An object of the invention is to alleviate the above drawbacks by providing a synthesizable synchronous static RAM using a combination of custom and semi-custom blocks.
Another object of the invention is to improve the access of an synchronous static RAM.
Yet another object of the invention is to provide relatively easy testability.
Still another object of the invention is to provide asynchronous initialization.
A further object of the invention is to provide memory modeling at the RTL level.
Yet another object of the invention is to enable automatic layout and thereby reduce design time.
To achieve the above objectives, the invention provides a synthesizable, synchronous static RAM which may include custom-built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section. The control clock generation section may be connected to the semi-custom built decoder and I/O section. Further, the arrangement of the above components may provide high speed access, easy testability and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell-based memory design.
The custom-built memory cells in bit slice may be compatible with semi-custom synthesis tools and standard cell layout design rules for simulation and automatic layout to thereby reduce design time. The memory cell and input/output/precharge section in the bit slice may include a single column of memory cells connected to common bit lines. The semi-custom decoder may include flip-flops at its output for reducing occurrences of glitches reaching the custom-built memory cells. The flip-flops may be driven by clock tree signals to reduce clock skew and address setup time to thereby improve operational speed.
The decoder may be a fully synthesizable block for which an RTL is available. Further, the semi-custom decoder may include buffers to improve the speed of access. Also, the custom built memory cells, semi-custom decoder, input/output section and semi-custom clock generation circuitry may be collectively and individually testable using register transfer level (RTL) models for each unit.
In addition, the flip-flops may be provided with a common asynchronous preset/clear input to enable simultaneous selection of all word lines and thereby all memory locations for writing common initialization values (i.e., the value at the data input port) at all memory locations. The asynchronous preset/clear signal may also be used to provide asynchronous resetting. Also, the flip-flops can be used to select multiple word lines simultaneously, thus providing a synchronous initialization through scan inputs. Other inputs may be used to provide a checker board test pattern initialization. The RTL code may be mapped over any technology library, whether high speed, low power, low leakage, etc. Further, the decoder may be tested using automatically generated test patterns via the scan input.


REFERENCES:
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5963454 (1999-10-01), Dockser et al.
patent: 6295627 (2001-09-01), Gowni et al.

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