Synchronous type flip-flop circuit of semiconductor device

Details Synchronous type flip-flop circuit of semiconductor device Synchronous type flip-flop circuit of semiconductor device

2000-11-30

2002-05-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S233100

Reexamination Certificate

active

06385106

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous type flip-flop circuit of a semiconductor device, and more particularly to a synchronous type flip-flop circuit capable of achieving high-speed operation while having a reduced size with respect to known synchronous type flip-flop circuits, so as to cope with semiconductor devices having a reduced size while using an increased clock speed.
2. Description of Related Art
Generally, a flip-flop circuit is a memory device having two stable states. In such a flip-flop circuit, a selected one of two stable states is activated in response to an input selecting that stable state, and this activated stable state is maintained until an input selecting the other stable state is applied. A synchronous type flip-flop circuit is a flip-flop circuit for inputting or outputting a signal in sync with a clock applied to a clock pulse input terminal thereof.
Referring to
FIGS. 1
to
3
, various configurations of a conventional synchronous type flip-flop circuit used in semiconductor devices are illustrated, respectively.
FIGS. 1 and 2
show conventional synchronous type flip-flop circuits using clock buffers, respectively.
FIG. 3
shows another synchronous type flip-flop circuit using transfer gates and clock buffers.
The conventional synchronous type flip-flop circuit illustrated in
FIG. 1
includes a first clock buffer unit
10
for outputting a signal of a ‘high’ level to a node Nd
1
in a ‘low’ level of a clock signal clk when an input signal D has a ‘low’ level, while outputting a signal of a ‘low’ level to the node Nd
1
in a ‘high’ level of the clock signal clk when the input signal D has a ‘high’ level, and a second clock buffer unit
12
for outputting a signal of a ‘high’ level to a node Nd
2
in the ‘low’ level of the clock signal clk when the node Nd
1
is at a ‘low’ level, while outputting a signal of a ‘low’ level to the node Nd
2
in the ‘high’ level of the clock signal clk when the node Nd
1
is at a ‘high’ level. The flip-flop circuit also includes a third clock buffer unit
14
for outputting a signal of a ‘high’ level to a node Nd
3
in the ‘low’ level of the clock signal clk when the node Nd
2
is at a ‘low’ level, while outputting a signal of a ‘low’ level to the node Nd
3
in the ‘high’ level of the clock signal clk when the node Nd
2
is at a ‘high’ level, a fourth clock buffer unit
16
for outputting a signal of a ‘high’ level to an output node Nd
4
in the ‘low’ level of the clock signal clk when the node Nd
3
is at a ‘low’ level, while outputting a signal of a ‘low’ level to the output node Nd
4
in the ‘high’ level of the clock signal clk when the node Nd
3
is at a ‘high’ level, and an inverter INV
1
coupled between the output node Nd
4
and another output node Nd
5
.
The first clock buffer unit
10
includes a PMOS transistor P
1
adapted to supply a supply voltage to the node Nd
1
in the ‘low’ level of the clock signal clk, and a pair of NMOS transistors N
1
and N
2
connected in series between the node Nd
1
and a ground voltage. The NMOS transistor NI receives the input signal D at the gate thereof whereas the NMOS transistor N
2
receives the clock signal clk at the gate thereof. Accordingly, the first clock buffer unit
10
outputs a ‘high’ signal to the node Nd
1
in the ‘low’ level of the clock signal clk in response to the ‘low’ level of the input signal D while outputting a ‘low’ signal to the node Nd
1
in the ‘high’ level of the clock signal clk in response to the ‘high’ level of the input signal D.
The second clock buffer unit
12
includes a PMOS transistor P
2
adapted to supply the supply voltage to the node Nd
2
in the ‘low’ level of the clock signal clk, and a pair of NMOS transistors N
3
and N
4
connected in series between the node Nd
2
and the ground voltage. The NMOS transistor N
3
receives the clock signal clk at the gate thereof whereas the NMOS transistor N
4
receives a signal from the node Nd
1
at the gate thereof. Accordingly, the second clock buffer unit
12
outputs a ‘high’ signal to the node Nd
2
in the ‘low’ level of the clock signal clk in response to the ‘low’ level of the node Nd
1
while outputting a ‘low’ signal to the node Nd
2
in the ‘high’ level of the clock signal clk in response to the ‘high’ level of the node Nd
1
.
The third clock buffer unit
14
includes a PMOS transistor P
3
activated in the ‘low’ level of the clock signal clk, and another PMOS transistor P
4
activated at the ‘low’ level of the node Nd
2
. The PMOS transistors P
3
and P
4
serve to supply the supply voltage to the node Nd
3
. The third clock buffer unit
14
also includes an NMOS transistor N
5
for discharging the potential of the node Nd
3
to the ground voltage in the ‘high’ level of the clock signal clk. By this configuration, the third clock buffer unit
14
outputs a ‘high’ signal to the node Nd
3
in the ‘low’ level of the clock signal clk in response to the ‘low’ level of the node Nd
2
while outputting a ‘low’ signal to the node Nd
3
in the ‘high’ level of the clock signal clk in response to the ‘high’ level of the node Nd
2
.
The fourth clock buffer unit
16
includes a PMOS transistor P
5
activated at the ‘low’ level of the node Nd
3
, and another PMOS transistor P
6
activated in the ‘low’ level of the clock signal clk. The PMOS transistors P
3
and P
4
serve to supply the supply voltage to the output node Nd
4
. The fourth clock buffer unit
16
also includes an NMOS transistor N
6
for discharging the potential of the output node Nd
4
to the ground voltage in the ‘high’ level of the clock signal clk. By this configuration, the fourth clock buffer unit
16
outputs a ‘high’ signal to the output node Nd
4
in the ‘low’ level of the clock signal clk in response to the ‘low’ level of the node Nd
3
while outputting a ‘low’ signal to the output node Nd
4
in the ‘high’ level of the clock signal clk in response to the ‘high’ level of the node Nd
3
.
The conventional synchronous type flip-flop circuit illustrated in
FIG. 2
includes a first clock buffer unit
20
for outputting a signal of a ‘high’ level to a node Nd
6
in a ‘low’ level of a clock signal clk when an input signal D has a ‘low’ level, while outputting a signal of a ‘low’ level to the node Nd
6
in a ‘high’ level of the clock signal clk when the input signal D has a ‘high’ level, and a second clock buffer unit
22
for outputting a signal of a ‘high’ level to a node Nd
7
in the ‘low’ level of the clock signal clk when the node Nd
6
is at a ‘low’ level, while outputting a signal of a ‘low’ level to the node Nd
7
in the ‘high’ level of the clock signal clk when the node Nd
6
is at a ‘high’ level. The flip-flop circuit also includes a third clock buffer unit
24
for outputting a signal of a ‘high’ level to a node Nd
8
in the ‘low’ level of the clock signal clk when the node Nd
7
is at a ‘low’ level, while outputting a signal of a ‘low’ level to the node Nd
8
in the ‘high’ level of the clock signal clk when the node Nd
7
is at a ‘high’ level, a fourth clock buffer unit
26
for outputting a signal of a ‘high’ level to an output node Nd
9
in the ‘low’ level of the clock signal clk when the node Nd
8
is at a ‘low’ level, while outputting a signal of a ‘low’ level to the output node Nd
9
in the ‘high’ level of the clock signal clk when the node Nd
8
is at a ‘high’ level, and an inverter INV
2
coupled between the output node Nd
9
and another output node Nd
10
.
The first clock buffer unit
20
includes a PMOS transistor P
7
adapted to supply a supply voltage to the node Nd
6
at the ‘low’ level of the input signal D, and a pair of NMOS transistors N
7
and N
8
connected in series between the node Nd
6
and a ground voltage. The NMOS transistor N
7
receives the clock signal clk at the gate thereof whereas the NMOS transistor N
8
receives the input signal D at the gate thereof. The first clock buffer unit
20
outputs a ‘high’ signal to the node Nd
6
in the ‘low’ level of the clock signal clk in response to the ‘low’ level of the input signal D whil

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