Synchronous to asynchronous to synchronous interface

Details Synchronous to asynchronous to synchronous interface Synchronous to asynchronous to synchronous interface

2005-01-25

2005-01-25

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S502000, C713S600000, C713S601000, C710S052000, C710S058000, C710S061000

Reexamination Certificate

active

06848060

ABSTRACT:
An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

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U.S. patent appln. Ser. No. 09/746,647 filed Dec. 21, 2000 to Peter W. Cook, Andy Davies, Stanley E. Schuster and Daniel Stasiak entitled “Asynchronous Pipeline Control Interface”.

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