Synchronous semiconductor memory having a burst transfer mode wi

Details Synchronous semiconductor memory having a burst transfer mode wi Synchronous semiconductor memory having a burst transfer mode wi

1996-11-29

1998-09-08

Swann, Tod R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518912, 36523004, 711105, G11C 700, G11C 800

Patent

active

058055045

ABSTRACT:
A synchronous semiconductor memory with a burst transfer mode is comprised of a plurality of memory cell subarrays. A plurality of internal data buses operates with an input buffer circuit to transfer data in parallel to the subarrays. The input buffer includes a shift register composed of a first and second cascade connected registers. A register output selector distributes the data signals in parallel to the plurality of internal buses.

REFERENCES:
patent: 4796231 (1989-01-01), Pinkham
patent: 5371714 (1994-12-01), Matsuda
patent: 5381367 (1995-01-01), Kajimoto
patent: 5384745 (1995-01-01), Konishi
patent: 5617555 (1997-04-01), Patel
H. Yoo et al., "FA 14.4: A 150MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods", IEEE, 1995, Session 14, pp. 250-251.

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