Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-08
2002-10-22
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S233100
Reexamination Certificate
active
06470467
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a synchronous semiconductor memory device operating in synchronization with an external clock signal.
2. Description of the Background Art
As an operation speed of the recent microprocessor (hereinafter abbreviated as an MPU) has been increased, to achieve rapid access by a Dynamic Random Access Memory (hereinafter abbreviated as a DRAM) or the like which is used as a main memory device, a synchronous DRAM (hereinafter abbreviated as an SDRAM) or the like which operates in synchronization with a clock signal is used.
In such SDRAM, a bank structure in which a memory cell array is divided into mutually independent banks is used to enable an operation at higher speed. More specifically, the operation is divided into row related and column relation operations which are independently controlled for every bank and, for example, these banks perform an interleave operation to reduce a precharge time or the like, so that a high speed operation is achieved.
For the above mentioned SDRAM, however, in order to further increase the speed of the operation, a so-called double data rate SDRAM (hereinafter abbreviated as a DDR-SDRAM) is achieved. In the DDR-SDRAM, data is not only output at an activation edge (which is for example a transition edge from “L” to “H” level) of an external clock signal, but also input/output in synchronization with an inactivation edge (which is for example a transition edge from “H” to “L” level). On the other hand, a conventional SDRAM in which data is input/output only in synchronization with the activation edge of the external clock signal is called a single data rate SDRAM (hereinafter abbreviated as an SDR-SDRAM).
As the operation speed of the semiconductor memory device such as the SDRAM increases as described above, there arises the following problem in the operation test during a manufacturing process or before shipping products.
More specifically, a very expensive tester device is required as the increase in the operation speed of the semiconductor memory device means that the operation speed of the tester device therefor must also be increased. This results in increase in a test cost. In other words, the manufacturing cost of the product disadvantageously increases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a synchronous semiconductor memory device capable of inexpensively performing an operation test while reducing the burden on a tester even in the case of the synchronous semiconductor memory device capable of operating at a high speed.
In short, the present invention is a synchronous semiconductor memory device which receives an address signal and a control signal in synchronization with an external clock signal and includes a memory cell array, internal synchronization signal generating circuit, address signal input circuit, address counter circuit, memory cell selecting circuit and data writing circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix. The internal synchronization signal generating circuit outputs a first internal clock signal in synchronization with the external clock signal in response to designation of a first operation mode, and outputs a second internal clock signal in synchronization with the external clock signal and having a frequency which is higher than that of the external clock signal in response to designation of a second operation mode.
The address signal input circuit receives the address signal in synchronization with the external clock signal. The address counter circuit generates internal address signals corresponding to the adjacent memory cells in accordance with the address signal over a prescribed number of cycles of an output from the internal synchronization signal generating circuit in time series.
The memory cell selecting circuit operates in accordance with the output from the internal synchronization signal generating circuit for selecting a memory cell in accordance with the internal address signal. The data writing circuit outputs a write data to the memory cell which has been selected by the memory cell selecting circuit.
The data writing circuit includes: an internal data generating circuit generating an internal write data which is sequentially inverted in synchronization with the second internal clock signal in accordance with a prescribed write data in the second operation mode; and a driving circuit outputting an output from the internal data generating circuit to the memory cell which is sequentially selected by the memory cell selecting circuit in the second operation mode.
According to another aspect of the present invention, a synchronous semiconductor memory device is provided which receives an address signal and a control signal in synchronization with an external clock signal and includes a memory cell array, internal synchronization signal generating circuit, address signal input circuit, address counter circuit, memory cell selecting circuit and data reading circuit.
The memory cell array includes a plurality of memory cells arranged in a matrix. The internal synchronization signal generating circuit outputs a first internal clock signal in synchronization with the external clock signal in response to designation of a first operation mode, and outputs a second internal clock signal in synchronization with the external clock signal and having a frequency which is higher than that of the external clock signal in response to designation of a second operation mode.
The address signal input circuit receives the address signal in synchronization with the external clock signal. The address counter circuit sequentially generates internal address signals by the number corresponding to a burst length in accordance with the address signal for every cycle of an output from the internal synchronization signal generating circuit.
The memory cell selecting circuit operates in accordance with the output from the internal synchronization signal generating circuit for selecting a memory cell in accordance with the internal address signal. The data reading circuit reads a data from the memory cell which has been selected by the memory cell selecting circuit.
The data reading circuit includes: a comparing circuit comparing a data which is sequentially read corresponding to the burst length and an expected value; and a count circuit counting a value of an internal address until the comparing circuit outputs a comparison result indicating mismatch.
Therefore, a main advantage of the present invention is that the burden on the tester can be reduced as the internal circuit operates at a speed which is higher than that of the external clock signal and internally generates and writes data which have been inverted between the adjacent memory cells in the second operation mode.
Another advantage of the present invention is that the internal circuit operates at a speed which is higher than that of the external clock signal, and that it is possible to detect an address to be burst read at which a defective bit is caused.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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Ooishi Tsukasa
Tomishima Shigeki
Chase Shelly A
De'cady Albert
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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