Synchronous semiconductor memory device capable of...

Details Synchronous semiconductor memory device capable of... Synchronous semiconductor memory device capable of...

1999-01-22

2001-05-08

Heckler, Thomas M. (Department: 2182)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Reexamination Certificate

active

06230280

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device operating in synchronization with a clock signal consisting of a series of externally supplied pulses, and more particularly to a configuration of an internal voltage generating circuit for generating an internal voltage.
2. Description of the Background Art
FIG. 22
is a diagram schematically showing an entire configuration of a conventional synchronous semiconductor device. Shown in
FIG. 22
is a configuration of a clock synchronous semiconductor memory device, as an example of a synchronous semiconductor device, which takes in an external signal and outputs data in synchronization with an external clock signal ext.CLK.
With reference to
FIG. 22
, a clock synchronous semiconductor memory device
100
includes a memory array
102
having a plurality of memory cells arranged in rows and columns; a clock input buffer
104
for buffering an externally supplied clock signal ext.CLK to generate an internal clock signal CLK; a command decoder
106
for taking in external control signals, i.e., a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, in synchronization with internal clock signal CLK from clock input buffer
104
, and generating an operation mode designating signal based on a combination of states of these control signals at a rising of internal clock signal CLK; and a control circuit
108
responsive to the operation mode designating signal from command decoder
106
for performing control necessary for execution of the designated operation mode in synchronization with internal clock signal CLK. Command decoder
106
determines the combination of the states of the control signals /RAS, /CAS and /WE at a rising of internal clock signal CLK, and generates the operation mode designating signal based on the result of determination. The combination of the states of these control signals is called a “command.”
Synchronous semiconductor memory device
100
further includes an address input buffer
110
for taking in an external address signal ADD and generating an internal address signal in synchronization with internal clock signal CLK under the control of control circuit
108
; a row selection circuit
112
operating under the control of control circuit
108
to drive an addressed row of memory array
102
to a selected state according to an internal row address signal supplied from address input buffer
110
; a column selection circuit
114
operating under the control of control circuit
108
to select a column of memory array
102
according to an internal column address signal from address input buffer
110
; a read circuit
116
for reading memory cell data on the column selected by column selection circuit
114
in synchronization with clock signal CLK under the control of control circuit
108
; and an output circuit
118
activated under the control of control circuit
108
for sequentially outputting data transferred from read circuit
116
.
Column selection circuit
114
changes the received column address signal in a prescribed sequence with the internal column address signal supplied from address input buffer
110
being a leading address, and sequentially selects columns of memory array
102
. Read circuit
116
reads and transfers data according to internal clock signal CLK under the control of control circuit
108
.
Output circuit
118
is supplied with a high voltage Vpp from an internal high voltage generating circuit
120
. This is because, as will be described later in detail, the last output stage of output circuit
118
is composed of n channel MOS transistors, and there is a need to prevent the voltage level reduction of the high level of the output data Q due to a threshold voltage loss of the n channel MOS transistor at the last output stage. Now, an operation of the dock synchronous semiconductor memory device shown in
FIG. 22
will be described with reference to a timing chart shown in FIG.
23
.
At arising of external clock signal ext.CLK in a clock cycle #1, row address strobe signal /RAS is set at a low (L) level and column address strobe signal /CAS and write enable signal /WE are each set at a high (H) level, and thus an active command is supplied. In response to the supplied active command, command decoder
106
generates and applies to control circuit
108
an array activation instructing signal. According to this array activation instructing signal, control circuit
108
causes address input buffer
110
to take in address signal ADD and to generate an internal row address signal X. Row selection circuit
112
operates under the control of control circuit
108
, and drives a word line corresponding to an addressed row of memory array
102
to a selected state according to the internal row address signal X (a word line is provided corresponding to each memory cell row).
When column address strobe signal /CAS is set at an L level and row address strobe signal /RAS and write enable signal /WE are set at an H level at a rising of external clock signal ext.CLK in clock cycle #3, a read command is supplied, which instructs data reading. According to a data reading designation signal from command decoder
106
, control circuit
108
causes address input buffer
110
to take in currently applied address signal ADD and to generate an internal column address signal Y.
Column selection circuit
114
sequentially selects columns in memory array
102
in a prescribed sequence with the address signal Y being a leading address. Data of the memory cell selected by column selection circuit
114
is transmitted to read circuit
116
. Read circuit
116
sequentially transfers the transmitted data in synchronization with internal clock signal CLK under the control of control circuit
108
, and provides the data to output circuit
118
. Output circuit
118
is then activated also under the control of control circuit
108
, and outputs the data supplied from read circuit
116
.
A certain period of time is required for the selection of a memory cell column by column selection circuit
114
as well as transfer of internal read data by read circuit
116
. Therefore, read data Q is set at a definite state at a rising of external clock signal ext.CLK in clock cycle #5 after two clock cycles since supplying of the read command. Thereafter, column selection circuit
114
sequentially selects memory cell columns in a prescribed sequence with address signal Y used as a leading address, and data in these memory cells are read out in synchroization with clock signal CLK. Data Q
1
, Q
2
and Q
3
become definite at rising of external clock signal ext.CLK in clock cycles #6, #7 and #8, respectively.
Output circuit
118
enters an output high impedance state after a prescribed number of data pieces are read out. The number of data pieces consecutively read out after a read command is supplied is called a burst length; the number of clock cycles required after supplying of the read command until a valid data is output is called a CAS latency.
Reading data out in synchronization with external clock signal ext.CLK enables to transfer data to a processor (not shown) in synchronization with the external clock signal ext.CLK, which permits high-speed data transfer. Accordingly, it becomes possible to prevent degradation of the performance of a processing system due to the difference in operating frequency between a processor and a main memory when a standard DRAM is used as the main memory.
Command decoder
106
may be configured to be supplied with a prescribed bit of address signal ADD. Clock input buffer
104
may be formed of a PLL (Phase Locked Loop), for example. Internal clock signal CLK has only to be a clock signal in synchronization with external clock signal ext.CLK.
FIG. 24
is a diagram schematically showing a configuration of the last stage of output circuit
118
shown in FIG.
22
. Referring to
FIG. 24
, output circuit
118
includes a level conversion circuit
118

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