Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1997-01-29

1998-10-13

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 365233, 326 56, G11C 700

Patent

active

058222545

ABSTRACT:
A semiconductor memory device of a synchronous type is disclosed, which has an output control circuit (14) adapted to output signals D2T and D2N by activating one of two conduction control signals D1T or by inactivating both of the conduction control signals in accordance with an output control signal MSK2B or OEB for controlling whether a data output terminal DQ is to be actuated or set into a high impedance, and an output circuit 17 provided with a couple of latch circuits 15 and 16 each adapted to individually latch and output the corresponding conduction control signals in synchronism with an internal synchronizing signal .phi.3. There is further provided an additional latch circuit 13 latching the output control signal in response to an inverted signal of the internal synchronizing signal .phi.3.

REFERENCES:
patent: 5043944 (1991-08-01), Nakamura et al.
patent: 5488581 (1996-01-01), Nagao et al.
patent: 5666071 (1997-09-01), Hawkins et al.

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